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SN74LV540ADWR

Public Made by Adom

by adom

Texas Instruments Buffers, Drivers, Receivers, Transceivers, SOIC-20-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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SN74LV540ADWR

Texas Instruments · Buffers, Drivers, Receivers, Transceivers · SOIC-20-300mil

SN74LV540ADWR from Texas Instruments, in a SOIC-20-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 OE1 input Active-low output enable 1; when it is high, all eight outputs are forced into the high-impedance state.
2 A1 input Buffer data input A1; inputs are tolerant to 5.5 V at any valid VCC.
3 A2 input Buffer data input A2; inputs are tolerant to 5.5 V at any valid VCC.
4 A3 input Buffer data input A3; inputs are tolerant to 5.5 V at any valid VCC.
5 A4 input Buffer data input A4; inputs are tolerant to 5.5 V at any valid VCC.
6 A5 input Buffer data input A5; inputs are tolerant to 5.5 V at any valid VCC.
7 A6 input Buffer data input A6; inputs are tolerant to 5.5 V at any valid VCC.
8 A7 input Buffer data input A7; inputs are tolerant to 5.5 V at any valid VCC.
9 A8 input Buffer data input A8; inputs are tolerant to 5.5 V at any valid VCC.
10 GND power_in Ground pin for the device.
11 Y8 tri_state Three-state buffer output Y8 that provides inverted data when enabled and is high-impedance when OE1 or OE2 is high.
12 Y7 tri_state Three-state buffer output Y7 that provides inverted data when enabled and is high-impedance when OE1 or OE2 is high.
13 Y6 tri_state Three-state buffer output Y6 that provides inverted data when enabled and is high-impedance when OE1 or OE2 is high.
14 Y5 tri_state Three-state buffer output Y5 that provides inverted data when enabled and is high-impedance when OE1 or OE2 is high.
15 Y4 tri_state Three-state buffer output Y4 that provides inverted data when enabled and is high-impedance when OE1 or OE2 is high.
16 Y3 tri_state Three-state buffer output Y3 that provides inverted data when enabled and is high-impedance when OE1 or OE2 is high.
17 Y2 tri_state Three-state buffer output Y2 that provides inverted data when enabled and is high-impedance when OE1 or OE2 is high.
18 Y1 tri_state Three-state buffer output Y1 that provides inverted data when enabled and is high-impedance when OE1 or OE2 is high.
19 OE2 input Active-low output enable 2; when it is high, all eight outputs are forced into the high-impedance state.
20 VCC power_in Supply pin; the device operates from 2 V to 5.5 V and each VCC pin should have a bypass capacitor placed close to it.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-20-300mil
Category Logic
Pins 20

CAD (KiCad official)

  • Symbol: SN74LV540ADWR
  • Footprint: Package_SO:SOIC-20W_7.5x12.8mm_P1.27mm
  • 3D model: SOIC-20-300mil (KiCad packages3D, STEP)
  • 3D model files: sn74lv540adwr-etched.step / sn74lv540adwr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74lv540adwr.step / sn74lv540adwr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (29 pp, sha256 93d06dbc8af80287, retrieved 2026-10-09, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF