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SN74LV374ATPWR

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Texas Instruments Flip Flops, TSSOP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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SN74LV374ATPWR

Texas Instruments · Flip Flops · TSSOP-20

SN74LV374ATPWR from Texas Instruments, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 OE input Buffered active-low output enable: when high, all eight Q outputs are forced to the high-impedance state, and OE should be tied to VCC through a pullup resistor to keep the outputs high-impedance during power up or power down.
2 1Q tri_state 3-state output of flip-flop 1 that takes the level of 1D on the positive CLK transition, with recommended IOH of -16 mA and IOL of 16 mA at VCC = 4.5 V to 5.5 V.
3 1D input Data input of flip-flop 1 that is latched on the positive transition of CLK and is TTL-voltage compatible.
4 2D input Data input of flip-flop 2 that is latched on the positive transition of CLK and is TTL-voltage compatible.
5 2Q tri_state 3-state output of flip-flop 2 that takes the level of 2D on the positive CLK transition, with recommended IOH of -16 mA and IOL of 16 mA at VCC = 4.5 V to 5.5 V.
6 3Q tri_state 3-state output of flip-flop 3 that takes the level of 3D on the positive CLK transition, with recommended IOH of -16 mA and IOL of 16 mA at VCC = 4.5 V to 5.5 V.
7 3D input Data input of flip-flop 3 that is latched on the positive transition of CLK and is TTL-voltage compatible.
8 4D input Data input of flip-flop 4 that is latched on the positive transition of CLK and is TTL-voltage compatible.
9 4Q tri_state 3-state output of flip-flop 4 that takes the level of 4D on the positive CLK transition, with recommended IOH of -16 mA and IOL of 16 mA at VCC = 4.5 V to 5.5 V.
10 GND power_in Ground reference pin for the device.
11 CLK input Clock input; the Q outputs are set to the logic levels present on the D inputs on its positive transition.
12 5Q tri_state 3-state output of flip-flop 5 that takes the level of 5D on the positive CLK transition, with recommended IOH of -16 mA and IOL of 16 mA at VCC = 4.5 V to 5.5 V.
13 5D input Data input of flip-flop 5 that is latched on the positive transition of CLK and is TTL-voltage compatible.
14 6D input Data input of flip-flop 6 that is latched on the positive transition of CLK and is TTL-voltage compatible.
15 6Q tri_state 3-state output of flip-flop 6 that takes the level of 6D on the positive CLK transition, with recommended IOH of -16 mA and IOL of 16 mA at VCC = 4.5 V to 5.5 V.
16 7Q tri_state 3-state output of flip-flop 7 that takes the level of 7D on the positive CLK transition, with recommended IOH of -16 mA and IOL of 16 mA at VCC = 4.5 V to 5.5 V.
17 7D input Data input of flip-flop 7 that is latched on the positive transition of CLK and is TTL-voltage compatible.
18 8D input Data input of flip-flop 8 that is latched on the positive transition of CLK and is TTL-voltage compatible.
19 8Q tri_state 3-state output of flip-flop 8 that takes the level of 8D on the positive CLK transition, with recommended IOH of -16 mA and IOL of 16 mA at VCC = 4.5 V to 5.5 V.
20 VCC power_in Supply voltage pin; the recommended operating range is 4.5 V to 5.5 V.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package TSSOP-20
Category Logic
Pins 20

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VCC 4.5 5.5 V 3
High-level input voltage VIH 2 V VCC = 4.5 V to 5.5 V 3
Low-level input voltage VIL 0.8 V VCC = 4.5 V to 5.5 V 3
Input voltage VI 0 5.5 V 3
Output voltage VO 0 5.5 V 3-state 3
High-level output current IOH -16 mA VCC = 4.5 V to 5.5 V 3
Low-level output current IOL 16 mA VCC = 4.5 V to 5.5 V 3
Input transition rise or fall rate Δt/Δv 20 ns/V VCC = 4.5 V to 5.5 V 3
Operating free-air temperature TA -40 125 °C 3
Supply voltage range VCC -0.5 7 V 3
Input voltage range VI -0.5 7 V 3
Voltage applied to any output in the high-impedance or power-off state VO -0.5 7 V high-impedance or power-off state 3
Output voltage range VO -0.5 V 3
Input clamp current IIK -20 20 mA VI < 0 or VI > VCC 3
Output clamp current IOK -50 50 mA VO < 0 or VO > VCC 3
Continuous output current IO -35 35 mA VO = 0 to VCC 3
Continuous current through VCC or GND -70 70 mA 3
Storage temperature range Tstg -65 150 °C 3
High-level output voltage VOH 4.4 4.5 V IOH = -50 mA, VCC = 4.5 V, TA = 25°C 4
High-level output voltage VOH 4.4 V IOH = -50 mA, VCC = 4.5 V, TA = -40°C to 125°C 4
High-level output voltage VOH 3.8 V IOH = -16 mA, VCC = 4.5 V, TA = 25°C 4
Low-level output voltage VOL 0 0.1 V IOL = 50 mA, VCC = 4.5 V, TA = 25°C 4
Low-level output voltage VOL 0.1 V IOL = 50 mA, VCC = 4.5 V, TA = -40°C to 125°C 4
Low-level output voltage VOL 0.55 V IOL = 16 mA, VCC = 4.5 V, TA = 25°C 4
Input current II -1 0.1 1 mA VI = 5.5 V or GND, VCC = 0 to 5.5 V, TA = 25°C 4
Off-state (high-impedance) output current IOZ -2.5 0.25 2.5 mA VO = VCC or GND, VCC = 5.5 V, TA = 25°C 4
Quiescent supply current ICC 2 20 mA VI = VCC or GND, IO = 0, VCC = 5.5 V, TA = 25°C 4
Supply current increase per TTL-level input ΔICC 40 50 mA One input at 3.4 V, other inputs at VCC or GND, VCC = 5.5 V, TA = 25°C 4
Partial power-down current Ioff 0 0.5 mA VI or VO = 0 to 5.5 V, TA = 25°C 4
Partial power-down current Ioff 5 mA VI or VO = 0 to 5.5 V, TA = -40°C to 125°C 4
Clock frequency fclock 90 MHz CL = 15 pF, VCC = 5 V ± 0.5 V, TA = 25°C 4
Clock frequency fclock 70 MHz CL = 15 pF, VCC = 5 V ± 0.5 V, TA = -40°C to 125°C 4
Clock frequency fclock 85 MHz CL = 50 pF, VCC = 5 V ± 0.5 V, TA = 25°C 4
Clock frequency fclock 65 MHz CL = 50 pF, VCC = 5 V ± 0.5 V, TA = -40°C to 125°C 4
Pulse duration, CLK high or low tw 6.5 ns VCC = 5 V ± 0.5 V, TA = 25°C 4
Pulse duration, CLK high or low tw 8.5 ns VCC = 5 V ± 0.5 V, TA = -40°C to 125°C 4
Setup time, data before CLK↑ tsu 2.5 ns VCC = 5 V ± 0.5 V, TA = 25°C 4
Setup time, data before CLK↑ tsu 5 ns VCC = 5 V ± 0.5 V, TA = -40°C to 125°C 4
Hold time, data after CLK↑ th 2.5 ns VCC = 5 V ± 0.5 V, TA = 25°C 4
Maximum clock frequency fmax 90 140 MHz CL = 15 pF, VCC = 5 V ± 0.5 V, TA = 25°C 4
Maximum clock frequency fmax 70 MHz CL = 15 pF, VCC = 5 V ± 0.5 V, TA = -40°C to 125°C 4
Maximum clock frequency fmax 85 150 MHz CL = 50 pF, VCC = 5 V ± 0.5 V, TA = 25°C 4
Maximum clock frequency fmax 65 MHz CL = 50 pF, VCC = 5 V ± 0.5 V, TA = -40°C to 125°C 4
Propagation delay CLK to Q tpd 3 4.9 8.1 ns CL = 15 pF, VCC = 5 V ± 0.5 V, TA = 25°C 4
Propagation delay CLK to Q tpd 1 11 ns CL = 15 pF, VCC = 5 V ± 0.5 V, TA = -40°C to 125°C 4
Enable time OE to Q ten 3.2 4.6 7.6 ns CL = 15 pF, VCC = 5 V ± 0.5 V, TA = 25°C 4
Enable time OE to Q ten 1 12 ns CL = 15 pF, VCC = 5 V ± 0.5 V, TA = -40°C to 125°C 4
Disable time OE to Q tdis 1.7 3.4 6.8 ns CL = 15 pF, VCC = 5 V ± 0.5 V, TA = 25°C 4
Disable time OE to Q tdis 1 9 ns CL = 15 pF, VCC = 5 V ± 0.5 V, TA = -40°C to 125°C 4
Propagation delay CLK to Q tpd 4.2 5.9 10.1 ns CL = 50 pF, VCC = 5 V ± 0.5 V, TA = 25°C 4
Propagation delay CLK to Q tpd 1 13 ns CL = 50 pF, VCC = 5 V ± 0.5 V, TA = -40°C to 125°C 4
Enable time OE to Q ten 4.5 5.5 9.6 ns CL = 50 pF, VCC = 5 V ± 0.5 V, TA = 25°C 4
Enable time OE to Q ten 1 13 ns CL = 50 pF, VCC = 5 V ± 0.5 V, TA = -40°C to 125°C 4
Disable time OE to Q tdis 2.4 4 8.8 ns CL = 50 pF, VCC = 5 V ± 0.5 V, TA = 25°C 4
Disable time OE to Q tdis 1 12.5 ns CL = 50 pF, VCC = 5 V ± 0.5 V, TA = -40°C to 125°C 4
Output skew tsk(o) 1 4
Package thermal impedance, PW package θJA 83 °C/W PW package, per JESD 51-7 3

CAD (KiCad official)

  • Symbol: SN74LV374ATPWR
  • Footprint: Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm
  • 3D model: TSSOP-20 (KiCad packages3D, STEP)
  • 3D model files: sn74lv374atpwr-etched.step / sn74lv374atpwr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74lv374atpwr.step / sn74lv374atpwr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (18 pp, sha256 67fd4533b284e0b4, retrieved 2026-10-18, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF