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SN74LV374APWR
Public Made by Adomby adom
Texas Instruments Flip Flops, TSSOP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+56@@ -0,0 +1,56 @@+# SN74LV374APWR++**Texas Instruments** · Flip Flops · TSSOP-20++SN74LV374APWR from Texas Instruments, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | OE | input | Output enable input; when low enables normal output logic states, when high places all 8 outputs in high-impedance state. |+| 2 | 1Q | tri_state | 3-state output 1; carries D1 logic level captured on rising CLK edge when OE is low, high-impedance when OE is high. |+| 3 | 1D | input | D-type data input 1; logic level captured by flip-flop on rising edge of CLK. |+| 4 | 2D | input | D-type data input 2; logic level captured by flip-flop on rising edge of CLK. |+| 5 | 2Q | tri_state | 3-state output 2; carries D2 logic level captured on rising CLK edge when OE is low, high-impedance when OE is high. |+| 6 | 3Q | tri_state | 3-state output 3; carries D3 logic level captured on rising CLK edge when OE is low, high-impedance when OE is high. |+| 7 | 3D | input | D-type data input 3; logic level captured by flip-flop on rising edge of CLK. |+| 8 | 4D | input | D-type data input 4; logic level captured by flip-flop on rising edge of CLK. |+| 9 | 4Q | tri_state | 3-state output 4; carries D4 logic level captured on rising CLK edge when OE is low, high-impedance when OE is high. |+| 10 | GND | power_in | Ground reference pin; 0 V potential. |+| 11 | CLK | input | Clock input; on positive edge transition, D inputs are latched to Q outputs; minimum pulse width 5 ns at VCC = 5 V. |+| 12 | 5Q | tri_state | 3-state output 5; carries D5 logic level captured on rising CLK edge when OE is low, high-impedance when OE is high. |+| 13 | 5D | input | D-type data input 5; logic level captured by flip-flop on rising edge of CLK. |+| 14 | 6D | input | D-type data input 6; logic level captured by flip-flop on rising edge of CLK. |+| 15 | 6Q | tri_state | 3-state output 6; carries D6 logic level captured on rising CLK edge when OE is low, high-impedance when OE is high. |+| 16 | 7Q | tri_state | 3-state output 7; carries D7 logic level captured on rising CLK edge when OE is low, high-impedance when OE is high. |+| 17 | 7D | input | D-type data input 7; logic level captured by flip-flop on rising edge of CLK. |+| 18 | 8D | input | D-type data input 8; logic level captured by flip-flop on rising edge of CLK. |+| 19 | 8Q | tri_state | 3-state output 8; carries D8 logic level captured on rising CLK edge when OE is low, high-impedance when OE is high. |+| 20 | VCC | power_in | Power supply pin; operating voltage range 2 V to 5.5 V. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | TSSOP-20 |+| Category | Logic |+| Pins | 20 |++## CAD (KiCad official)++- Symbol: `SN74LV374APWR`+- Footprint: `Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm`+- 3D model: TSSOP-20 (KiCad packages3D, STEP)+- 3D model files: `sn74lv374apwr-etched.step` / `sn74lv374apwr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `sn74lv374apwr.step` / `sn74lv374apwr.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/lit/ds/symlink/sn74lv374a.pdf) (30 pp, sha256 `7a440a5280268468`, retrieved 2026-10-05, tier: manufacturer)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/sn74lv374apwr-datasheet.pdf)
page.jsonadded+230@@ -0,0 +1,230 @@+{+ "slug": "sn74lv374apwr",+ "version": "0.1.0",+ "type": "component",+ "description": "Texas Instruments Flip Flops, TSSOP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "logic",+ "sn74lv374apwr",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "sn74lv374apwr.kicad_sym",+ "sn74lv374apwr.kicad_mod",+ "sn74lv374apwr.glb",+ "sn74lv374apwr.step",+ "sn74lv374apwr.lbr",+ "docs/hero.png",+ "docs/sn74lv374apwr-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html",+ "sn74lv374apwr-hero.glb",+ "sn74lv374apwr-hero.overlay.json"+ ],+ "component": {+ "mpn": "SN74LV374APWR",+ "manufacturer": "Texas Instruments",+ "package": "TSSOP-20",+ "pin_count": 20,+ "category": "Logic",+ "subcategory": "Flip Flops",+ "datasheet": "https://www.ti.com/lit/ds/symlink/sn74lv374a.pdf",+ "parts": {+ "symbol": "sn74lv374apwr.kicad_sym",+ "footprint": "sn74lv374apwr.kicad_mod",+ "model_3d": "sn74lv374apwr-hero.glb",+ "model_3d_plain": "sn74lv374apwr.glb",+ "model_3d_step": "sn74lv374apwr-etched.step",+ "model_3d_step_plain": "sn74lv374apwr.step",+ "lbr": "sn74lv374apwr.lbr"+ },+ "distributor_links": {+ "lcsc": 2652836,+ "digikey": "296-3820-2-ND",+ "mouser": "595-SN74LV374APWR"+ },+ "distributor_check": {+ "checked_at": "2026-10-05T23:56:17Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": "296-3820-2-ND",+ "status": "found",+ "lifecycle": "Active"+ },+ "mouser": {+ "pn": "595-SN74LV374APWR",+ "status": "found"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "OE",+ "type": "input",+ "description": "Output enable input; when low enables normal output logic states, when high places all 8 outputs in high-impedance state."+ },+ {+ "number": "2",+ "name": "1Q",+ "type": "tri_state",+ "description": "3-state output 1; carries D1 logic level captured on rising CLK edge when OE is low, high-impedance when OE is high."+ },+ {+ "number": "3",+ "name": "1D",+ "type": "input",+ "description": "D-type data input 1; logic level captured by flip-flop on rising edge of CLK."+ },+ {+ "number": "4",+ "name": "2D",+ "type": "input",+ "description": "D-type data input 2; logic level captured by flip-flop on rising edge of CLK."+ },+ {+ "number": "5",+ "name": "2Q",+ "type": "tri_state",+ "description": "3-state output 2; carries D2 logic level captured on rising CLK edge when OE is low, high-impedance when OE is high."+ },+ {+ "number": "6",+ "name": "3Q",+ "type": "tri_state",+ "description": "3-state output 3; carries D3 logic level captured on rising CLK edge when OE is low, high-impedance when OE is high."+ },+ {+ "number": "7",+ "name": "3D",+ "type": "input",+ "description": "D-type data input 3; logic level captured by flip-flop on rising edge of CLK."+ },+ {+ "number": "8",+ "name": "4D",+ "type": "input",+ "description": "D-type data input 4; logic level captured by flip-flop on rising edge of CLK."+ },+ {+ "number": "9",+ "name": "4Q",+ "type": "tri_state",+ "description": "3-state output 4; carries D4 logic level captured on rising CLK edge when OE is low, high-impedance when OE is high."+ },+ {+ "number": "10",+ "name": "GND",+ "type": "power_in",+ "description": "Ground reference pin; 0 V potential."+ },+ {+ "number": "11",+ "name": "CLK",+ "type": "input",+ "description": "Clock input; on positive edge transition, D inputs are latched to Q outputs; minimum pulse width 5 ns at VCC = 5 V."+ },+ {+ "number": "12",+ "name": "5Q",+ "type": "tri_state",+ "description": "3-state output 5; carries D5 logic level captured on rising CLK edge when OE is low, high-impedance when OE is high."+ },+ {+ "number": "13",+ "name": "5D",+ "type": "input",+ "description": "D-type data input 5; logic level captured by flip-flop on rising edge of CLK."+ },+ {+ "number": "14",+ "name": "6D",+ "type": "input",+ "description": "D-type data input 6; logic level captured by flip-flop on rising edge of CLK."+ },+ {+ "number": "15",+ "name": "6Q",+ "type": "tri_state",+ "description": "3-state output 6; carries D6 logic level captured on rising CLK edge when OE is low, high-impedance when OE is high."+ },+ {+ "number": "16",+ "name": "7Q",+ "type": "tri_state",+ "description": "3-state output 7; carries D7 logic level captured on rising CLK edge when OE is low, high-impedance when OE is high."+ },+ {+ "number": "17",+ "name": "7D",+ "type": "input",+ "description": "D-type data input 7; logic level captured by flip-flop on rising edge of CLK."+ },+ {+ "number": "18",+ "name": "8D",+ "type": "input",+ "description": "D-type data input 8; logic level captured by flip-flop on rising edge of CLK."+ },+ {+ "number": "19",+ "name": "8Q",+ "type": "tri_state",+ "description": "3-state output 8; carries D8 logic level captured on rising CLK edge when OE is low, high-impedance when OE is high."+ },+ {+ "number": "20",+ "name": "VCC",+ "type": "power_in",+ "description": "Power supply pin; operating voltage range 2 V to 5.5 V."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-4-5-20251001",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [],+ "pages_sent": 30,+ "cost_usd": 0.1532,+ "at": "2026-10-05T23:55:59"+ },+ "datasheet": {+ "url": "https://www.ti.com/lit/ds/symlink/sn74lv374a.pdf",+ "pages": 30,+ "sha256": "7a440a5280268468",+ "source_tier": "mfr"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 20,+ "described": 20,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ }+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}