Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity

3D Model

Open in new tab ↗

Loads on click. Unloads only if this page sits in the background.

Symbol & Footprint

Schematic Symbol

Open full view ↗

Loads on click. Unloads only if this page sits in the background.

PCB Footprint

Open full view ↗

Loads on click. Unloads only if this page sits in the background.

Datasheet

Open in new tab ↗

Loads on click. Unloads only if this page sits in the background.

Download PDF

Contents

Pinout
Key specifications
CAD (KiCad official)
Provenance

README

markdown

SN74LV374APWR

Texas Instruments · Flip Flops · TSSOP-20

SN74LV374APWR from Texas Instruments, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	OE	input	Output enable input; when low enables normal output logic states, when high places all 8 outputs in high-impedance state.
2	1Q	tri_state	3-state output 1; carries D1 logic level captured on rising CLK edge when OE is low, high-impedance when OE is high.
3	1D	input	D-type data input 1; logic level captured by flip-flop on rising edge of CLK.
4	2D	input	D-type data input 2; logic level captured by flip-flop on rising edge of CLK.
5	2Q	tri_state	3-state output 2; carries D2 logic level captured on rising CLK edge when OE is low, high-impedance when OE is high.
6	3Q	tri_state	3-state output 3; carries D3 logic level captured on rising CLK edge when OE is low, high-impedance when OE is high.
7	3D	input	D-type data input 3; logic level captured by flip-flop on rising edge of CLK.
8	4D	input	D-type data input 4; logic level captured by flip-flop on rising edge of CLK.
9	4Q	tri_state	3-state output 4; carries D4 logic level captured on rising CLK edge when OE is low, high-impedance when OE is high.
10	GND	power_in	Ground reference pin; 0 V potential.
11	CLK	input	Clock input; on positive edge transition, D inputs are latched to Q outputs; minimum pulse width 5 ns at VCC = 5 V.
12	5Q	tri_state	3-state output 5; carries D5 logic level captured on rising CLK edge when OE is low, high-impedance when OE is high.
13	5D	input	D-type data input 5; logic level captured by flip-flop on rising edge of CLK.
14	6D	input	D-type data input 6; logic level captured by flip-flop on rising edge of CLK.
15	6Q	tri_state	3-state output 6; carries D6 logic level captured on rising CLK edge when OE is low, high-impedance when OE is high.
16	7Q	tri_state	3-state output 7; carries D7 logic level captured on rising CLK edge when OE is low, high-impedance when OE is high.
17	7D	input	D-type data input 7; logic level captured by flip-flop on rising edge of CLK.
18	8D	input	D-type data input 8; logic level captured by flip-flop on rising edge of CLK.
19	8Q	tri_state	3-state output 8; carries D8 logic level captured on rising CLK edge when OE is low, high-impedance when OE is high.
20	VCC	power_in	Power supply pin; operating voltage range 2 V to 5.5 V.

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	TSSOP-20
Category	Logic
Pins	20

CAD (KiCad official)

Symbol: SN74LV374APWR
Footprint: Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm
3D model: TSSOP-20 (KiCad packages3D, STEP)
3D model files: sn74lv374apwr-etched.step / sn74lv374apwr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74lv374apwr.step / sn74lv374apwr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (30 pp, sha256 7a440a5280268468, retrieved 2026-10-05, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF