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SN74LV373ATPWR
Public Made by Adomby adom
Texas Instruments Latches, TSSOP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
| Name | Last updated |
|---|---|
| docs | 18d ago |
| viewers | 18d ago |
| package.json | 9d ago |
| page.json | 9d ago |
| README.md | 18d ago |
| sn74lv373atpwr-etched.glb | 9d ago |
| sn74lv373atpwr-etched.step | 9d ago |
| sn74lv373atpwr-hero.glb | 9d ago |
| sn74lv373atpwr-hero.overlay.json | 9d ago |
| sn74lv373atpwr.glb | 18d ago |
| sn74lv373atpwr.kicad_mod | 18d ago |
| sn74lv373atpwr.kicad_sym | 18d ago |
| sn74lv373atpwr.lbr | 18d ago |
| sn74lv373atpwr.step | 18d ago |
SN74LV373ATPWR
Texas Instruments · Latches · TSSOP-20
SN74LV373ATPWR from Texas Instruments, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | OE | input | Active-low output enable: when low the eight Q outputs follow the latches, and when high they are forced to the high-impedance state; tie OE to VCC through a pullup resistor to keep outputs high-Z during power-up and power-down. |
| 2 | 1Q | tri_state | Three-state latch output 1; sources up to IOH = -16 mA and sinks up to IOL = 16 mA at VCC = 4.5 V to 5.5 V, and is high-impedance while OE is high. |
| 3 | 1D | input | Data input to latch 1, TTL-voltage compatible; the latched value is taken when LE falls, with setup time of 1.5 ns and hold time of 3.5 ns. |
| 4 | 2D | input | Data input to latch 2, TTL-voltage compatible; the latched value is taken when LE falls, with setup time of 1.5 ns and hold time of 3.5 ns. |
| 5 | 2Q | tri_state | Three-state latch output 2; sources up to IOH = -16 mA and sinks up to IOL = 16 mA at VCC = 4.5 V to 5.5 V, and is high-impedance while OE is high. |
| 6 | 3Q | tri_state | Three-state latch output 3; sources up to IOH = -16 mA and sinks up to IOL = 16 mA at VCC = 4.5 V to 5.5 V, and is high-impedance while OE is high. |
| 7 | 3D | input | Data input to latch 3, TTL-voltage compatible; the latched value is taken when LE falls, with setup time of 1.5 ns and hold time of 3.5 ns. |
| 8 | 4D | input | Data input to latch 4, TTL-voltage compatible; the latched value is taken when LE falls, with setup time of 1.5 ns and hold time of 3.5 ns. |
| 9 | 4Q | tri_state | Three-state latch output 4; sources up to IOH = -16 mA and sinks up to IOL = 16 mA at VCC = 4.5 V to 5.5 V, and is high-impedance while OE is high. |
| 10 | GND | power_in | Device ground reference; unused inputs must be held at VCC or GND for proper operation. |
| 11 | LE | input | Latch enable: while LE is high the Q outputs follow the D inputs, and when LE is taken low the Q outputs latch the levels present at D. |
| 12 | 5Q | tri_state | Three-state latch output 5; sources up to IOH = -16 mA and sinks up to IOL = 16 mA at VCC = 4.5 V to 5.5 V, and is high-impedance while OE is high. |
| 13 | 5D | input | Data input to latch 5, TTL-voltage compatible; the latched value is taken when LE falls, with setup time of 1.5 ns and hold time of 3.5 ns. |
| 14 | 6D | input | Data input to latch 6, TTL-voltage compatible; the latched value is taken when LE falls, with setup time of 1.5 ns and hold time of 3.5 ns. |
| 15 | 6Q | tri_state | Three-state latch output 6; sources up to IOH = -16 mA and sinks up to IOL = 16 mA at VCC = 4.5 V to 5.5 V, and is high-impedance while OE is high. |
| 16 | 7Q | tri_state | Three-state latch output 7; sources up to IOH = -16 mA and sinks up to IOL = 16 mA at VCC = 4.5 V to 5.5 V, and is high-impedance while OE is high. |
| 17 | 7D | input | Data input to latch 7, TTL-voltage compatible; the latched value is taken when LE falls, with setup time of 1.5 ns and hold time of 3.5 ns. |
| 18 | 8D | input | Data input to latch 8, TTL-voltage compatible; the latched value is taken when LE falls, with setup time of 1.5 ns and hold time of 3.5 ns. |
| 19 | 8Q | tri_state | Three-state latch output 8; sources up to IOH = -16 mA and sinks up to IOL = 16 mA at VCC = 4.5 V to 5.5 V, and is high-impedance while OE is high. |
| 20 | VCC | power_in | Supply voltage; recommended operating range is 4.5 V to 5.5 V, with an absolute maximum of 7 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | TSSOP-20 |
| Category | Logic |
| Pins | 20 |
CAD (KiCad official)
- Symbol:
SN74LV373ATPWR - Footprint:
Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm - 3D model: TSSOP-20 (KiCad packages3D, STEP)
- 3D model files:
sn74lv373atpwr-etched.step/sn74lv373atpwr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);sn74lv373atpwr.step/sn74lv373atpwr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (18 pp, sha256
0a6a0b048c3ece7d, retrieved 2026-10-11, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).