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SN74LV373ADWR

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Texas Instruments Latches, SOIC-20-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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SN74LV373ADWR

Texas Instruments · Latches · SOIC-20-300mil

SN74LV373ADWR from Texas Instruments, in a SOIC-20-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 OE input Buffered output enable input; when low enables normal output logic states, when high places all Q outputs in high-impedance state.
2 1Q tri_state First latch Q output; follows 1D input when LE is high, retains latched state when LE is low.
3 1D input First latch D input; data is accepted and appears at 1Q output when LE is high.
4 2D input Second latch D input; data is accepted and appears at 2Q output when LE is high.
5 2Q tri_state Second latch Q output; follows 2D input when LE is high, retains latched state when LE is low.
6 3Q tri_state Third latch Q output; follows 3D input when LE is high, retains latched state when LE is low.
7 3D input Third latch D input; data is accepted and appears at 3Q output when LE is high.
8 4D input Fourth latch D input; data is accepted and appears at 4Q output when LE is high.
9 4Q tri_state Fourth latch Q output; follows 4D input when LE is high, retains latched state when LE is low.
10 GND power_in Ground reference, 0 V potential.
11 LE input Latch enable input; when high, Q outputs follow D inputs; when low, Q outputs are latched at current D logic levels.
12 5Q tri_state Fifth latch Q output; follows 5D input when LE is high, retains latched state when LE is low.
13 5D input Fifth latch D input; data is accepted and appears at 5Q output when LE is high.
14 6D input Sixth latch D input; data is accepted and appears at 6Q output when LE is high.
15 6Q tri_state Sixth latch Q output; follows 6D input when LE is high, retains latched state when LE is low.
16 7Q tri_state Seventh latch Q output; follows 7D input when LE is high, retains latched state when LE is low.
17 7D input Seventh latch D input; data is accepted and appears at 7Q output when LE is high.
18 8D input Eighth latch D input; data is accepted and appears at 8Q output when LE is high.
19 8Q tri_state Eighth latch Q output; follows 8D input when LE is high, retains latched state when LE is low.
20 VCC power_in Positive power supply; recommended operating voltage range 2 V to 5.5 V per section 5.3.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-20-300mil
Category Logic ICs
Pins 20

CAD (KiCad official)

  • Symbol: SN74LV373ADWR
  • Footprint: Package_SO:SOIC-20W_7.5x12.8mm_P1.27mm
  • 3D model: SOIC-20-300mil (KiCad packages3D, STEP)
  • 3D model files: sn74lv373adwr-etched.step / sn74lv373adwr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74lv373adwr.step / sn74lv373adwr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (33 pp, sha256 a5bbe6c5c890d2af, retrieved 2026-10-07, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF