# SN74LV32ATPWRG4Q1

**Texas Instruments** · Logic Gates · TSSOP-14

SN74LV32ATPWRG4Q1 from Texas Instruments, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1A | input | Input A of gate 1 of the quadruple 2-input positive-OR gate (Y = A + B); recommended input voltage range is 0 V to 5.5 V and unused inputs must be held at VCC or GND. |
| 2 | 1B | input | Input B of gate 1 of the quadruple 2-input positive-OR gate (Y = A + B); recommended input voltage range is 0 V to 5.5 V and unused inputs must be held at VCC or GND. |
| 3 | 1Y | output | Output of gate 1, equal to A + B; output voltage range is 0 V to VCC and continuous output current is limited to ±25 mA. |
| 4 | 2A | input | Input A of gate 2 (Y = A + B); recommended input voltage range is 0 V to 5.5 V and unused inputs must be held at VCC or GND. |
| 5 | 2B | input | Input B of gate 2 (Y = A + B); recommended input voltage range is 0 V to 5.5 V and unused inputs must be held at VCC or GND. |
| 6 | 2Y | output | Output of gate 2, equal to A + B; output voltage range is 0 V to VCC and continuous output current is limited to ±25 mA. |
| 7 | GND | power_in | Ground reference pin for the device. |
| 8 | 3Y | output | Output of gate 3, equal to A + B; output voltage range is 0 V to VCC and continuous output current is limited to ±25 mA. |
| 9 | 3A | input | Input A of gate 3 (Y = A + B); recommended input voltage range is 0 V to 5.5 V and unused inputs must be held at VCC or GND. |
| 10 | 3B | input | Input B of gate 3 (Y = A + B); recommended input voltage range is 0 V to 5.5 V and unused inputs must be held at VCC or GND. |
| 11 | 4Y | output | Output of gate 4, equal to A + B; output voltage range is 0 V to VCC and continuous output current is limited to ±25 mA. |
| 12 | 4A | input | Input A of gate 4 (Y = A + B); recommended input voltage range is 0 V to 5.5 V and unused inputs must be held at VCC or GND. |
| 13 | 4B | input | Input B of gate 4 (Y = A + B); recommended input voltage range is 0 V to 5.5 V and unused inputs must be held at VCC or GND. |
| 14 | VCC | power_in | Supply voltage, recommended operating range 2 V to 5.5 V. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | TSSOP-14 |
| Category | Logic |
| Pins | 14 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage range | VCC | -0.5 |  | 7 | V |  | 4 |
| Input voltage range | VI | -0.5 |  | 7 | V |  | 4 |
| Voltage applied to any output in the high-impedance or power-off state | VO | -0.5 |  | 7 | V |  | 4 |
| Output voltage range | VO | -0.5 |  |  | V | Upper limit printed as VCC + 0.5 V; not numeric | 4 |
| Input clamp current | IIK | -20 |  |  | mA | VI < 0 | 4 |
| Output clamp current | IOK | -50 |  |  | mA | VO < 0 | 4 |
| Continuous output current | IO | -25 |  | 25 | mA | VO = 0 to VCC | 4 |
| Continuous current through VCC or GND |  | -50 |  | 50 | mA |  | 4 |
| Storage temperature | Tstg | -65 |  | 150 | °C |  | 4 |
| Supply voltage | VCC | 2 |  | 5.5 | V |  | 4 |
| High-level input voltage | VIH | 1.5 |  |  | V | VCC = 2 V | 4 |
| Low-level input voltage | VIL |  |  | 0.5 | V | VCC = 2 V | 4 |
| Input voltage | VI | 0 |  | 5.5 | V |  | 4 |
| Output voltage | VO | 0 |  |  | V | Upper limit printed as VCC; not numeric | 4 |
| High-level output current | IOH | -50 |  |  | μA | VCC = 2 V | 4 |
| High-level output current | IOH | -2 |  |  | mA | VCC = 2.3 V to 2.7 V | 4 |
| High-level output current | IOH | -6 |  |  | mA | VCC = 3 V to 3.6 V | 4 |
| High-level output current | IOH | -12 |  |  | mA | VCC = 4.5 V to 5.5 V | 4 |
| Low-level output current | IOL |  |  | 50 | μA | VCC = 2 V | 5 |
| Low-level output current | IOL |  |  | 2 | mA | VCC = 2.3 V to 2.7 V | 5 |
| Low-level output current | IOL |  |  | 6 | mA | VCC = 3 V to 3.6 V | 5 |
| Low-level output current | IOL |  |  | 12 | mA | VCC = 4.5 V to 5.5 V | 5 |
| Input transition rise or fall rate | ∆t/∆v |  |  | 200 | ns/V | VCC = 2.3 V to 2.7 V | 5 |
| Input transition rise or fall rate | ∆t/∆v |  |  | 100 | ns/V | VCC = 3 V to 3.6 V | 5 |
| Input transition rise or fall rate | ∆t/∆v |  |  | 20 | ns/V | VCC = 4.5 V to 5.5 V | 5 |
| Operating free-air temperature | TA | -40 |  | 105 | °C |  | 5 |
| Junction-to-ambient thermal resistance | RθJA |  | 113 |  | °C/W | PW (TSSOP), 14 pins | 5 |
| High level output voltage | VOH | 2 |  |  | V | IOH = -2 mA, VCC = 2.3 V | 5 |
| High level output voltage | VOH | 2.48 |  |  | V | IOH = -6 mA, VCC = 3 V | 5 |
| High level output voltage | VOH | 3.8 |  |  | V | IOH = -12 mA, VCC = 4.5 V | 5 |
| Low level output voltage | VOL |  |  | 0.1 | V | IOL = 50 μA, VCC = 2 to 5.5 V | 5 |
| Low level output voltage | VOL |  |  | 0.4 | V | IOL = 2 mA, VCC = 2.3 V | 5 |
| Low level output voltage | VOL |  |  | 0.44 | V | IOL = 6 mA, VCC = 3 V | 5 |
| Low level output voltage | VOL |  |  | 0.55 | V | IOL = 12 mA, VCC = 4.5 V | 5 |
| Input leakage current | II | -1 |  | 1 | μA | VI = 5.5 V or GND, VCC = 0 to 5.5 V | 5 |
| Supply current | ICC |  |  | 20 | μA | VI = VCC or GND, IO = 0, VCC = 5.5 V | 5 |
| Input/Output Power-Off Leakage Current | Ioff |  |  | 5 | μA | VI or VO = 0 to 5.5 V, VCC = 0 | 5 |
| Propagation delay tpd, A or B to Y | tpd |  |  | 20 | ns | VCC = 2.5 V ±0.2 V, CL = 50 pF, full recommended temperature range | 5 |
| Propagation delay tpd, A or B to Y | tpd |  |  | 13 | ns | VCC = 3.3 V ±0.3 V, CL = 50 pF, full recommended temperature range | 6 |
| Propagation delay tpd, A or B to Y | tpd |  |  | 8.5 | ns | VCC = 5 V ±0.5 V, CL = 50 pF, full recommended temperature range | 6 |
| Quiet output, maximum dynamic VOL | VOL(P) |  | 0.2 | 0.8 | V | VCC = 3.3 V, CL = 50 pF, TA = 25°C | 6 |
| Quiet output, minimum dynamic VOL | VOL(V) | -0.8 | -0.1 |  | V | VCC = 3.3 V, CL = 50 pF, TA = 25°C | 6 |
| Quiet output, minimum dynamic VOH | VOH(V) | 3.1 |  |  | V | VCC = 3.3 V, CL = 50 pF, TA = 25°C | 6 |
| High-level dynamic input voltage | VIH(D) | 2.31 |  |  | V | VCC = 3.3 V, CL = 50 pF, TA = 25°C | 6 |
| Low-level dynamic input voltage | VIL(D) |  |  | 0.99 | V | VCC = 3.3 V, CL = 50 pF, TA = 25°C | 6 |

## CAD (KiCad official)

- Symbol: `SN74LV32ATPWRG4Q1`
- Footprint: `Package_SO:TSSOP-14_4.4x5mm_P0.65mm`
- 3D model: TSSOP-14 (KiCad packages3D, STEP)
- 3D model files: `sn74lv32atpwrg4q1-etched.step` / `sn74lv32atpwrg4q1-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `sn74lv32atpwrg4q1.step` / `sn74lv32atpwrg4q1.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/sn74lv32a-q1) (17 pp, sha256 `626ccbae269f5ee2`, retrieved 2026-10-18, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/sn74lv32atpwrg4q1-datasheet.pdf)