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SN74LV32AMPWREP

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Texas Instruments Logic Gates, TSSOP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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SN74LV32AMPWREP

Texas Instruments · Logic Gates · TSSOP-14

SN74LV32AMPWREP from Texas Instruments, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1A input Data input A of gate 1 (Y = A + B); the datasheet requires unused inputs to be held at VCC or GND, and input voltage is specified as 0 to 5.5 V.
2 1B input Data input B of gate 1 (Y = A + B); the datasheet requires unused inputs to be held at VCC or GND, and input voltage is specified as 0 to 5.5 V.
3 1Y output Output of gate 1 (Y = A + B); continuous output current is limited to ±25 mA, and the Ioff circuitry disables the output during partial power-down.
4 2A input Data input A of gate 2 (Y = A + B); the datasheet requires unused inputs to be held at VCC or GND, and input voltage is specified as 0 to 5.5 V.
5 2B input Data input B of gate 2 (Y = A + B); the datasheet requires unused inputs to be held at VCC or GND, and input voltage is specified as 0 to 5.5 V.
6 2Y output Output of gate 2 (Y = A + B); continuous output current is limited to ±25 mA, and the Ioff circuitry disables the output during partial power-down.
7 GND power_in Ground reference for the device; unused inputs must be tied to GND or VCC.
8 3Y output Output of gate 3 (Y = A + B); continuous output current is limited to ±25 mA, and the Ioff circuitry disables the output during partial power-down.
9 3A input Data input A of gate 3 (Y = A + B); the datasheet requires unused inputs to be held at VCC or GND, and input voltage is specified as 0 to 5.5 V.
10 3B input Data input B of gate 3 (Y = A + B); the datasheet requires unused inputs to be held at VCC or GND, and input voltage is specified as 0 to 5.5 V.
11 4Y output Output of gate 4 (Y = A + B); continuous output current is limited to ±25 mA, and the Ioff circuitry disables the output during partial power-down.
12 4A input Data input A of gate 4 (Y = A + B); the datasheet requires unused inputs to be held at VCC or GND, and input voltage is specified as 0 to 5.5 V.
13 4B input Data input B of gate 4 (Y = A + B); the datasheet requires unused inputs to be held at VCC or GND, and input voltage is specified as 0 to 5.5 V.
14 VCC power_in Supply voltage, 2 V to 5.5 V recommended operating range.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package TSSOP-14
Category Logic
Pins 14

CAD (KiCad official)

  • Symbol: SN74LV32AMPWREP
  • Footprint: Package_SO:TSSOP-14_4.4x5mm_P0.65mm
  • 3D model: TSSOP-14 (KiCad packages3D, STEP)
  • 3D model files: sn74lv32ampwrep-etched.step / sn74lv32ampwrep-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74lv32ampwrep.step / sn74lv32ampwrep.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (14 pp, sha256 ffb8b096b71814bb, retrieved 2026-10-11, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF