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SN74LV273APWRG4

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Texas Instruments Flip Flops, TSSOP-20. Datasheet-verified pinout, KiCad symbol/footprint/3D.

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Contents

README

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SN74LV273APWRG4

Texas Instruments · Flip Flops · TSSOP-20

SN74LV273APWRG4 from Texas Instruments, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CLR input Asynchronous active-low clear input that forces all Q outputs to logic low when pulled low, independent of clock state.
2 1Q output Q output of flip-flop 1; latches data from 1D input on rising edge of CLK when CLR is high.
3 1D input Data input for flip-flop 1; data is latched to Q output on rising edge of CLK when CLR is high.
4 2D input Data input for flip-flop 2; data is latched to Q output on rising edge of CLK when CLR is high.
5 2Q output Q output of flip-flop 2; latches data from 2D input on rising edge of CLK when CLR is high.
6 3Q output Q output of flip-flop 3; latches data from 3D input on rising edge of CLK when CLR is high.
7 3D input Data input for flip-flop 3; data is latched to Q output on rising edge of CLK when CLR is high.
8 4D input Data input for flip-flop 4; data is latched to Q output on rising edge of CLK when CLR is high.
9 4Q output Q output of flip-flop 4; latches data from 4D input on rising edge of CLK when CLR is high.
10 GND power_in Ground reference pin providing 0V return path for device operation.
11 CLK input Clock input, positive-edge triggered; latches data from all D inputs to corresponding Q outputs on rising edge.
12 5Q output Q output of flip-flop 5; latches data from 5D input on rising edge of CLK when CLR is high.
13 5D input Data input for flip-flop 5; data is latched to Q output on rising edge of CLK when CLR is high.
14 6D input Data input for flip-flop 6; data is latched to Q output on rising edge of CLK when CLR is high.
15 6Q output Q output of flip-flop 6; latches data from 6D input on rising edge of CLK when CLR is high.
16 7Q output Q output of flip-flop 7; latches data from 7D input on rising edge of CLK when CLR is high.
17 7D input Data input for flip-flop 7; data is latched to Q output on rising edge of CLK when CLR is high.
18 8D input Data input for flip-flop 8; data is latched to Q output on rising edge of CLK when CLR is high.
19 8Q output Q output of flip-flop 8; latches data from 8D input on rising edge of CLK when CLR is high.
20 VCC power_in Positive power supply pin; operating voltage range 2V to 5.5V per recommended operating conditions.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package TSSOP-20
Category Logic
Pins 20

CAD (KiCad official)

  • Symbol: SN74LV273APWRG4
  • Footprint: Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm
  • 3D model: TSSOP-20 (KiCad packages3D, STEP)
  • 3D model files: sn74lv273apwrg4-etched.step / sn74lv273apwrg4-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74lv273apwrg4.step / sn74lv273apwrg4.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (42 pp, sha256 840685afe1407bf8, retrieved 2026-09-23, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF