component

SN74LV273ADWR

Public Made by Adom

by adom

Texas Instruments Flip Flops, SOIC-20-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentlogic icssn74lv273adwrfactory-2.0.0extractor-text

Verified SN74LV273ADWR

by Ray · last 31 Oct 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

31 Oct 2026RayPublished by the parts factory: tier mfr, 20 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: SN74LV273ADWR · SOIC-20-300mil · 20 pins
  • ✓copper: 20 copper pads, none touching another net
  • ✓datasheet: all 20 pin names found in the 23-page datasheet
  • ✓distributor: lcsc C7790, digikey 296-14904-2-ND, mouser 595-SN74LV273ADWR
  • ✓family: SOIC-20W_7.5x12.8mm_P1.27mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-vi6r4s57/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): the datasheet dimensions give no height or body size to compare
  • ✓pads: 20 pins = 20 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 20 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ sn74lv273adwr.kicad_sym✓ sn74lv273adwr.kicad_mod✓ sn74lv273adwr.step
Spot something wrong? Report it as an issue Propose a fix Records are signed by members of adom.
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity
main
Download ZIP Propose a change
Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 6h ago
viewers sn74lv273adwr: viewers · Ray 6h ago
package.json Publish 0.1.0 · Ray 6h ago
page.json Set visibility: public · Ray 6h ago
README.md Publish 0.1.0 · Ray 6h ago
sn74lv273adwr-etched.glb Publish 0.1.0 · Ray 6h ago
sn74lv273adwr-etched.step sn74lv273adwr: factory component page (tier=mfr) · Ray 6h ago
sn74lv273adwr-hero.glb sn74lv273adwr: hero GLB from the etched model (keeps the MPN mark) · Ray 6h ago
sn74lv273adwr-hero.overlay.json Publish 0.1.0 · Ray 6h ago
sn74lv273adwr.glb Publish 0.1.0 · Ray 6h ago
sn74lv273adwr.kicad_mod Publish 0.1.0 · Ray 6h ago
sn74lv273adwr.kicad_sym Publish 0.1.0 · Ray 6h ago
sn74lv273adwr.lbr Publish 0.1.0 · Ray 6h ago
sn74lv273adwr.step Publish 0.1.0 · Ray 6h ago
verification.json Verified: Published by the parts factory: tier mfr, 20 pins · Ray 5h ago

SN74LV273ADWR

Texas Instruments · Flip Flops · SOIC-20-300mil

SN74LV273ADWR from Texas Instruments, in a SOIC-20-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CLR input Direct clear input; a low level forces all Q outputs low regardless of CLK and D.
2 1Q output Flip-flop 1 output, rated for IOH/IOL of ±12 mA at VCC = 4.5 V to 5.5 V.
3 1D input Flip-flop 1 data input, transferred to 1Q on the positive-going CLK edge.
4 2D input Flip-flop 2 data input, transferred to 2Q on the positive-going CLK edge.
5 2Q output Flip-flop 2 output, rated for IOH/IOL of ±12 mA at VCC = 4.5 V to 5.5 V.
6 3Q output Flip-flop 3 output, rated for IOH/IOL of ±12 mA at VCC = 4.5 V to 5.5 V.
7 3D input Flip-flop 3 data input, transferred to 3Q on the positive-going CLK edge.
8 4D input Flip-flop 4 data input, transferred to 4Q on the positive-going CLK edge.
9 4Q output Flip-flop 4 output, rated for IOH/IOL of ±12 mA at VCC = 4.5 V to 5.5 V.
10 GND power_in Ground pin; continuous current through VCC or GND is limited to ±50 mA.
11 CLK input Clock input; data is transferred to the Q outputs on the positive-going edge.
12 5Q output Flip-flop 5 output, rated for IOH/IOL of ±12 mA at VCC = 4.5 V to 5.5 V.
13 5D input Flip-flop 5 data input, transferred to 5Q on the positive-going CLK edge.
14 6D input Flip-flop 6 data input, transferred to 6Q on the positive-going CLK edge.
15 6Q output Flip-flop 6 output, rated for IOH/IOL of ±12 mA at VCC = 4.5 V to 5.5 V.
16 7Q output Flip-flop 7 output, rated for IOH/IOL of ±12 mA at VCC = 4.5 V to 5.5 V.
17 7D input Flip-flop 7 data input, transferred to 7Q on the positive-going CLK edge.
18 8D input Flip-flop 8 data input, transferred to 8Q on the positive-going CLK edge.
19 8Q output Flip-flop 8 output, rated for IOH/IOL of ±12 mA at VCC = 4.5 V to 5.5 V.
20 VCC power_in Supply voltage, 2 V to 5.5 V recommended operating range (absolute maximum 7 V).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-20-300mil
Category Logic ICs
Pins 20

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VCC 2 5.5 V 4
High-level input voltage VIH 1.5 V VCC = 2 V 4
Low-level input voltage VIL 0.5 V VCC = 2 V 4
Input voltage VI 0 5.5 V 4
High-level output current IOH -50 µA VCC = 2 V 4
High-level output current IOH -2 mA VCC = 2.3 V to 2.7 V 4
High-level output current IOH -6 mA VCC = 3 V to 3.6 V 4
High-level output current IOH -12 mA VCC = 4.5 V to 5.5 V 4
Low-level output current IOL 50 µA VCC = 2 V 4
Low-level output current IOL 2 mA VCC = 2.3 V to 2.7 V 4
Low-level output current IOL 6 mA VCC = 3 V to 3.6 V 4
Low-level output current IOL 12 mA VCC = 4.5 V to 5.5 V 4
Input transition rise or fall rate Δt/Δv 200 ns/V VCC = 2.3 V to 2.7 V 4
Input transition rise or fall rate Δt/Δv 100 ns/V VCC = 3 V to 3.6 V 4
Input transition rise or fall rate Δt/Δv 20 ns/V VCC = 4.5 V to 5.5 V 4
Operating free-air temperature TA -40 85 °C 4
High-level output voltage VOH 2 V IOH = −2 mA, VCC = 2.3 V 4
High-level output voltage VOH 2.48 V IOH = −6 mA, VCC = 3 V 4
High-level output voltage VOH 3.8 V IOH = −12 mA, VCC = 4.5 V 4
Low-level output voltage VOL 0.1 V IOL = 50 µA, VCC = 2 V to 5.5 V 4
Low-level output voltage VOL 0.4 V IOL = 2 mA, VCC = 2.3 V 4
Low-level output voltage VOL 0.44 V IOL = 6 mA, VCC = 3 V 4
Low-level output voltage VOL 0.55 V IOL = 12 mA, VCC = 4.5 V 4
Input current II -1 1 µA VI = 5.5 V or GND, VCC = 0 to 5.5 V 4
Supply current ICC 20 µA VI = VCC or GND, IO = 0, VCC = 5.5 V 4
Partial power down current Ioff 5 µA VI or VO = 0 to 5.5 V, VCC = 0 4
Pulse duration, CLR low tw 7 ns VCC = 2.5 V ± 0.2 V 5
Pulse duration, CLK high or low tw 8.5 ns VCC = 2.5 V ± 0.2 V 5
Setup time, data before CLK↑ (Data) tsu 10.5 ns VCC = 2.5 V ± 0.2 V 5
Setup time, CLR inactive tsu 4 ns VCC = 2.5 V ± 0.2 V 5
Hold time, data after CLK↑ th 1 ns VCC = 2.5 V ± 0.2 V 5
Pulse duration, CLR low tw 6 ns VCC = 3.3 V ± 0.3 V 5
Pulse duration, CLK high or low tw 6.5 ns VCC = 3.3 V ± 0.3 V 5
Setup time, data before CLK↑ (Data) tsu 6.5 ns VCC = 3.3 V ± 0.3 V 5
Setup time, CLR inactive tsu 2.5 ns VCC = 3.3 V ± 0.3 V 5
Pulse duration, CLR low tw 5 ns VCC = 5 V ± 0.5 V 5
Pulse duration, CLK high or low tw 5 ns VCC = 5 V ± 0.5 V 5
Setup time, data before CLK↑ (Data) tsu 4.5 ns VCC = 5 V ± 0.5 V 5
Setup time, CLR inactive tsu 2 ns VCC = 5 V ± 0.5 V 5
Maximum clock frequency fmax 45 MHz VCC = 2.5 V ± 0.2 V, CL = 15 pF 5
Maximum clock frequency fmax 40 MHz VCC = 2.5 V ± 0.2 V, CL = 50 pF 5
Propagation delay CLK to Q tpd 1 20.5 ns VCC = 2.5 V ± 0.2 V, CL = 15 pF 5
Propagation delay CLR to Q tPHL 1 21 ns VCC = 2.5 V ± 0.2 V, CL = 15 pF 5
Propagation delay CLK to Q tpd 1 25 ns VCC = 2.5 V ± 0.2 V, CL = 50 pF 5
Propagation delay CLR to Q tPHL 1 25.5 ns VCC = 2.5 V ± 0.2 V, CL = 50 pF 5
Output skew tsk(o) 2 ns VCC = 2.5 V ± 0.2 V, CL = 50 pF 5
Maximum clock frequency fmax 65 MHz VCC = 3.3 V ± 0.3 V, CL = 15 pF 6
Maximum clock frequency fmax 45 MHz VCC = 3.3 V ± 0.3 V, CL = 50 pF 6
Propagation delay CLK to Q tpd 1 16 ns VCC = 3.3 V ± 0.3 V, CL = 15 pF 6
Propagation delay CLR to Q tPHL 1 16 ns VCC = 3.3 V ± 0.3 V, CL = 15 pF 6
Propagation delay CLK to Q tpd 1 19.5 ns VCC = 3.3 V ± 0.3 V, CL = 50 pF 6
Propagation delay CLR to Q tPHL 1 19.5 ns VCC = 3.3 V ± 0.3 V, CL = 50 pF 6
Output skew tsk(o) 1.5 ns VCC = 3.3 V ± 0.3 V, CL = 50 pF 6
Maximum clock frequency fmax 100 MHz VCC = 5 V ± 0.5 V, CL = 15 pF 6
Maximum clock frequency fmax 70 MHz VCC = 5 V ± 0.5 V, CL = 50 pF 6
Propagation delay CLK to Q tpd 1 10.5 ns VCC = 5 V ± 0.5 V, CL = 15 pF 6
Propagation delay CLR to Q tPHL 1 10 ns VCC = 5 V ± 0.5 V, CL = 15 pF 6
Propagation delay CLK to Q tpd 1 12.5 ns VCC = 5 V ± 0.5 V, CL = 50 pF 6
Propagation delay CLR to Q tPHL 1 12 ns VCC = 5 V ± 0.5 V, CL = 50 pF 6
Output skew tsk(o) 1 ns VCC = 5 V ± 0.5 V, CL = 50 pF 6
Supply voltage range VCC -0.5 7 V 3
Package thermal impedance θJA 58 °C/W DW package 3

CAD (KiCad official)

  • Symbol: SN74LV273ADWR
  • Footprint: Package_SO:SOIC-20W_7.5x12.8mm_P1.27mm
  • 3D model: SOIC-20-300mil (KiCad packages3D, STEP)
  • 3D model files: sn74lv273adwr-etched.step / sn74lv273adwr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74lv273adwr.step / sn74lv273adwr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (23 pp, sha256 0e82e9a3a5dfcf3c, retrieved 2026-10-31, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF