component
SN74LV21ADR
Public Made by Adomby adom
Texas Instruments Logic Gates, SOIC-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
| Name | Last updated |
|---|---|
| docs | 9h ago |
| viewers | 9h ago |
| package.json | 9h ago |
| page.json | 9h ago |
| README.md | 9h ago |
| sn74lv21adr-etched.glb | 9h ago |
| sn74lv21adr-etched.step | 9h ago |
| sn74lv21adr-hero.glb | 9h ago |
| sn74lv21adr-hero.overlay.json | 9h ago |
| sn74lv21adr.glb | 9h ago |
| sn74lv21adr.kicad_mod | 9h ago |
| sn74lv21adr.kicad_sym | 9h ago |
| sn74lv21adr.lbr | 9h ago |
| sn74lv21adr.step | 9h ago |
SN74LV21ADR
Texas Instruments · Logic Gates · SOIC-14
SN74LV21ADR from Texas Instruments, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1A | input | First input of AND gate 1; logic input voltage 0 to 5.5 V |
| 2 | 1B | input | Second input of AND gate 1; logic input voltage 0 to 5.5 V |
| 3 | NC | unconnected | Not internally connected |
| 4 | 1C | input | Third input of AND gate 1; logic input voltage 0 to 5.5 V |
| 5 | 1D | input | Fourth input of AND gate 1; logic input voltage 0 to 5.5 V |
| 6 | 1Y | output | Output of AND gate 1 (Y = 1A • 1B • 1C • 1D); output voltage 0 to VCC |
| 7 | GND | power_in | Ground reference, 0 V |
| 8 | 2Y | output | Output of AND gate 2 (Y = 2A • 2B • 2C • 2D); output voltage 0 to VCC |
| 9 | 2A | input | First input of AND gate 2; logic input voltage 0 to 5.5 V |
| 10 | 2B | input | Second input of AND gate 2; logic input voltage 0 to 5.5 V |
| 11 | NC | unconnected | Not internally connected |
| 12 | 2C | input | Third input of AND gate 2; logic input voltage 0 to 5.5 V |
| 13 | 2D | input | Fourth input of AND gate 2; logic input voltage 0 to 5.5 V |
| 14 | VCC | power_in | Positive supply voltage; 2 to 5.5 V |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-14 |
| Category | Logic |
| Pins | 14 |
CAD (KiCad official)
- Symbol:
SN74LV21ADR - Footprint:
Package_SO:SOIC-14_3.9x8.7mm_P1.27mm - 3D model: SOIC-14 (KiCad packages3D, STEP)
- 3D model files:
sn74lv21adr-etched.step/sn74lv21adr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);sn74lv21adr.step/sn74lv21adr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (25 pp, sha256
6cf9dce71cfece45, retrieved 2026-10-07, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-4-5-20251001(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).