component
SN74LV21ADR
Public Made by Adomby adom
Texas Instruments Logic Gates, SOIC-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+50@@ -0,0 +1,50 @@+# SN74LV21ADR++**Texas Instruments** · Logic Gates · SOIC-14++SN74LV21ADR from Texas Instruments, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | 1A | input | First input of AND gate 1; logic input voltage 0 to 5.5 V |+| 2 | 1B | input | Second input of AND gate 1; logic input voltage 0 to 5.5 V |+| 3 | NC | unconnected | Not internally connected |+| 4 | 1C | input | Third input of AND gate 1; logic input voltage 0 to 5.5 V |+| 5 | 1D | input | Fourth input of AND gate 1; logic input voltage 0 to 5.5 V |+| 6 | 1Y | output | Output of AND gate 1 (Y = 1A • 1B • 1C • 1D); output voltage 0 to VCC |+| 7 | GND | power_in | Ground reference, 0 V |+| 8 | 2Y | output | Output of AND gate 2 (Y = 2A • 2B • 2C • 2D); output voltage 0 to VCC |+| 9 | 2A | input | First input of AND gate 2; logic input voltage 0 to 5.5 V |+| 10 | 2B | input | Second input of AND gate 2; logic input voltage 0 to 5.5 V |+| 11 | NC | unconnected | Not internally connected |+| 12 | 2C | input | Third input of AND gate 2; logic input voltage 0 to 5.5 V |+| 13 | 2D | input | Fourth input of AND gate 2; logic input voltage 0 to 5.5 V |+| 14 | VCC | power_in | Positive supply voltage; 2 to 5.5 V |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | SOIC-14 |+| Category | Logic |+| Pins | 14 |++## CAD (KiCad official)++- Symbol: `SN74LV21ADR`+- Footprint: `Package_SO:SOIC-14_3.9x8.7mm_P1.27mm`+- 3D model: SOIC-14 (KiCad packages3D, STEP)+- 3D model files: `sn74lv21adr-etched.step` / `sn74lv21adr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `sn74lv21adr.step` / `sn74lv21adr.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/lit/ds/symlink/sn74lv21a.pdf) (25 pp, sha256 `6cf9dce71cfece45`, retrieved 2026-10-07, tier: manufacturer)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/sn74lv21adr-datasheet.pdf)
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logic input voltage 0 to 5.5 V"+ },+ {+ "number": "2",+ "name": "1B",+ "type": "input",+ "description": "Second input of AND gate 1; logic input voltage 0 to 5.5 V"+ },+ {+ "number": "3",+ "name": "NC",+ "type": "unconnected",+ "description": "Not internally connected"+ },+ {+ "number": "4",+ "name": "1C",+ "type": "input",+ "description": "Third input of AND gate 1; logic input voltage 0 to 5.5 V"+ },+ {+ "number": "5",+ "name": "1D",+ "type": "input",+ "description": "Fourth input of AND gate 1; logic input voltage 0 to 5.5 V"+ },+ {+ "number": "6",+ "name": "1Y",+ "type": "output",+ "description": "Output of AND gate 1 (Y = 1A • 1B • 1C • 1D); output voltage 0 to VCC"+ },+ {+ "number": "7",+ "name": "GND",+ "type": "power_in",+ "description": "Ground reference, 0 V"+ },+ {+ "number": "8",+ "name": "2Y",+ "type": "output",+ "description": "Output of AND gate 2 (Y = 2A • 2B • 2C • 2D); output voltage 0 to VCC"+ },+ {+ "number": "9",+ "name": "2A",+ "type": "input",+ "description": "First input of AND gate 2; logic input voltage 0 to 5.5 V"+ },+ {+ "number": "10",+ "name": "2B",+ "type": "input",+ "description": "Second input of AND gate 2; logic input voltage 0 to 5.5 V"+ },+ {+ "number": "11",+ "name": "NC",+ "type": "unconnected",+ "description": "Not internally connected"+ },+ {+ "number": "12",+ "name": "2C",+ "type": "input",+ "description": "Third input of AND gate 2; logic input voltage 0 to 5.5 V"+ },+ {+ "number": "13",+ "name": "2D",+ "type": "input",+ "description": "Fourth input of AND gate 2; logic input voltage 0 to 5.5 V"+ },+ {+ "number": "14",+ "name": "VCC",+ "type": "power_in",+ "description": "Positive supply voltage; 2 to 5.5 V"+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-4-5-20251001",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [],+ "pages_sent": 25,+ "cost_usd": 0.1257,+ "at": "2026-10-07T07:16:00"+ },+ "datasheet": {+ "url": "https://www.ti.com/lit/ds/symlink/sn74lv21a.pdf",+ "pages": 25,+ "sha256": "6cf9dce71cfece45",+ "source_tier": "mfr"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 14,+ "described": 14,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "sn74lv21adr.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 6,+ 8.7,+ 1.75+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "3b9a775da256c8afcc28dcddfbc2eb3f266107fe61ce8446d96f2c52b6f44a70",+ "checked": "2026-10-07",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "sn74lv21adr-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 6,+ 8.7,+ 1.75+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "625acd97044eab113708bcaad8b6ffe5125bff92695c041fc60b9cb1faa80b46",+ "checked": "2026-10-07",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}