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docs sn74lv1t04dckr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
viewers pin 1: carry the footprint's marker into the .lbr, the viewer and page.json (silk-marker, drawn, top-left) · Ray
package.json Publish 0.2.0 · Ray
pads.json pin 1: carry the footprint's marker into the .lbr, the viewer and page.json (silk-marker, drawn, top-left) · Ray
page.json sn74lv1t04dckr: white body in tscircuit (pre-1.8 etch structure under an assembly instance); Ray 2026-10-19: black IC b… · Ray
README.md sn74lv1t04dckr: laser-etched CAD + chip hero (factory 2.0.0 backfill) · Ray
sn74lv1t04dckr-etched.fit.json sn74lv1t04dckr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
sn74lv1t04dckr-etched.glb sn74lv1t04dckr: white body in tscircuit (pre-1.8 etch structure under an assembly instance); Ray 2026-10-19: black IC b… · Ray
sn74lv1t04dckr-etched.step sn74lv1t04dckr: white body in tscircuit (pre-1.8 etch structure under an assembly instance); Ray 2026-10-19: black IC b… · Ray
sn74lv1t04dckr.glb Publish 0.1.0 · Ray
sn74lv1t04dckr.kicad_mod Publish 0.1.0 · Ray
sn74lv1t04dckr.kicad_sym Publish 0.1.0 · Ray
sn74lv1t04dckr.lbr rebuild the library on adom-lbr 2.32.0. The published copy was built by 2.18.0, which imported every KiCad roundrect an… · Ray
sn74lv1t04dckr.step Publish 0.1.0 · Ray

SN74LV1T04DCKR

Texas Instruments · Inverters · SC-70-5

SN74LV1T04DCKR from Texas Instruments, in a SC-70-5. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 NC unconnected Not internally connected. May be left floating or tied to GND/VCC per board design.
2 A input Logic input A to the inverter. Reduced CMOS input thresholds (V_IH min ~1.35 V at 3.3 V V_CC; V_IL max ~0.8 V) allow direct interfacing from lower-voltage logic. 5-V tolerant regardless of V_CC.
3 GND power_in Ground reference (0 V) for the device.
4 Y output Inverted logic output (Y = /A), referenced to V_CC. Push-pull CMOS drive: 8 mA at 5 V, 7 mA at 3.3 V, 5 mA at 2.5 V, 3 mA at 1.8 V.
5 VCC power_in Positive supply rail. Operating range 1.6 V to 5.5 V (recommended); absolute max 7.0 V. Sets the output high level and defines the down-translation target rail.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SC-70-5
Category Logic
Pins 5

Ordering variants

Same part, different packaging or reel option.

  • SN74LV1T04DCKR
  • SN74LV1T04DCKRDCKT
  • SN74LV1T04DCKRDBVR
  • SN74LV1T04DCKRDBVT

CAD (KiCad official)

  • Symbol: SN74LV1T04DCKR
  • Footprint: Package_TO_SOT_SMD:SOT-353_SC-70-5
  • 3D model: SC-70-5 (KiCad packages3D, STEP)
  • 3D model files: sn74lv1t04dckr-etched.step / sn74lv1t04dckr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74lv1t04dckr.step / sn74lv1t04dckr.glb are the bare package body.

3D model downloads

Two STEP files. Same geometry, different body top:

File Size Use it when
sn74lv1t04dckr.step 87 KB You want the bare part, or you mark your own boards.
sn74lv1t04dckr-etched.step 2.1 MB You want the part with SN74LV1T04DCKR already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 534 faces against 102 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (26 pp, sha256 e13f07ae46199f2b, retrieved 2026-08-17, tier: manufacturer)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF