component

SN74LV166ADR

Public Made by Adom

by adom

Texas Instruments Shift Registers, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentlogicsn74lv166adrfactory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity

3D Model

Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.

Symbol & Footprint

Schematic Symbol

Open full view ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.

PCB Footprint

Open full view ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.

Datasheet

Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.
Download PDF
Contents

README

markdown

SN74LV166ADR

Texas Instruments · Shift Registers · SOIC-16

SN74LV166ADR from Texas Instruments, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 SER input Serial data input, enabled for serial shifting when SH/LD is high; Table 5-1 labels it "Serial Output", which conflicts with its function as the serial input.
2 A input Parallel data input A, loaded synchronously on the next CLK low-to-high edge when SH/LD is low.
3 B input Parallel data input B, loaded synchronously on the next CLK low-to-high edge when SH/LD is low.
4 C input Parallel data input C, loaded synchronously on the next CLK low-to-high edge when SH/LD is low.
5 D input Parallel data input D, loaded synchronously on the next CLK low-to-high edge when SH/LD is low.
6 CLK INH input Clock inhibit input; clocking is inhibited while it is held high and should only change to high while CLK is high.
7 CLK input Clock input; the register clocks on its low-to-high edge through a 2-input NOR gate with CLK INH.
8 GND power_in Ground reference pin.
9 CLR input Active-low clear input that overrides all other inputs, including CLK, and resets all flip-flops to zero.
10 E input Parallel data input E, loaded synchronously on the next CLK low-to-high edge when SH/LD is low.
11 F input Parallel data input F, loaded synchronously on the next CLK low-to-high edge when SH/LD is low.
12 G input Parallel data input G, loaded synchronously on the next CLK low-to-high edge when SH/LD is low.
13 QH output Serial data output from the last flip-flop (QH).
14 H input Parallel data input H, loaded synchronously on the next CLK low-to-high edge when SH/LD is low.
15 SH/LD input Shift/load input: high enables serial shifting, low loads the parallel data inputs on the next clock pulse.
16 VCC power_in Supply voltage pin, 2 V to 5.5 V per the recommended operating conditions; bypass with a 0.1 µF capacitor close to the pin.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-16
Category Logic
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VCC 2 5.5 V 4
High-level input voltage VIH 1.5 V VCC = 2 V 4
Low-level input voltage VIL 0.5 V VCC = 2 V 4
Input voltage VI 0 5.5 V 4
Output voltage VO 0 V 4
High-level output current IOH -50 µA VCC = 2 V 4
High-level output current IOH -2 mA VCC = 2.3 V to 2.7 V 4
High-level output current IOH -6 mA VCC = 3 V to 3.6 V 4
High-level output current IOH -12 mA VCC = 4.5 V to 5.5 V 4
Low-level output current IOL 50 µA VCC = 2 V 4
Low-level output current IOL 2 mA VCC = 2.3 V to 2.7 V 4
Low-level output current IOL 6 mA VCC = 3 V to 3.6 V 4
Low-level output current IOL 12 mA VCC = 4.5 V to 5.5 V 4
Input transition rise or fall rate Δt/Δv 200 ns/V VCC = 2.3 V to 2.7 V 5
Input transition rise or fall rate Δt/Δv 100 ns/V VCC = 3 V to 3.6 V 5
Input transition rise or fall rate Δt/Δv 20 ns/V VCC = 4.5 V to 5.5 V 5
Operating free-air temperature TA -40 85 °C 5
Supply voltage range VCC -0.5 7 V 4
Input voltage range VI -0.5 7 V 4
Output voltage range (high or low state) VO -0.5 V applied in high or low state 4
Output voltage range (power-off state) VO -0.5 7 V applied to any output in the power-off state 4
Input clamp current IIK -20 mA VI < 0 4
Output clamp current IOK -50 mA VO < 0 4
Continuous output current IO -25 25 mA VO = 0 to VCC 4
Continuous current through VCC or GND ICC/IGND -50 50 mA 4
Storage temperature Tstg -65 150 °C 4
High-level output voltage VOH 2 V IOH = −2 mA, VCC 2.3 V 5
High-level output voltage VOH 2.48 V IOH = −50 µA, VCC 3 V 5
High-level output voltage VOH 3.8 V IOH = −6 mA, VCC 4.5 V 5
Low-level output voltage VOL 0.1 V IOH = −12 mA, VCC 2 V to 5.5 V (as printed) 5
Low-level output voltage VOL 0.4 V VCC 2.3 V 5
Low-level output voltage VOL 0.44 V VCC 3 V 5
Low-level output voltage VOL 0.55 V IOL = 4 mA, VCC 4.5 V 5
Input current II -1 1 μA VI = VCC or 0, VCC 0 to 5.5 V 5
Quiescent supply current ICC 20 μA VI = VCC or 0, IO = 0, VCC 5.5 V 5
Partial-power-down leakage current Ioff 5 μA 5
Input capacitance Ci 1.6 pF VCC 3.3 V 5
Junction-to-ambient thermal resistance RθJA 73 °C/W D (SOIC) 16-pin package 5

CAD (KiCad official)

  • Symbol: SN74LV166ADR
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOIC-16 (KiCad packages3D, STEP)
  • 3D model files: sn74lv166adr-etched.step / sn74lv166adr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74lv166adr.step / sn74lv166adr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (28 pp, sha256 b75083ecee9d24d7, retrieved 2026-10-21, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF