component
SN74LV165AD
Public Made by Adomby adom
Texas Instruments Shift Registers, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
| Name | Last updated |
|---|---|
| docs | 11d ago |
| viewers | 11d ago |
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| page.json | 11d ago |
| README.md | 11d ago |
| sn74lv165ad-etched.glb | 11d ago |
| sn74lv165ad-etched.step | 11d ago |
| sn74lv165ad-hero.glb | 11d ago |
| sn74lv165ad-hero.overlay.json | 11d ago |
| sn74lv165ad.glb | 11d ago |
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| sn74lv165ad.lbr | 11d ago |
| sn74lv165ad.step | 11d ago |
SN74LV165AD
Texas Instruments · Shift Registers · SOIC-16
SN74LV165AD from Texas Instruments, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | SH/LD | input | Load input; when low, it enables the eight direct parallel data inputs A through H to be loaded into the register. |
| 2 | CLK | input | Storage clock input that clocks the shift register, and CLK INH can inhibit this clock. |
| 3 | E | input | Serial/parallel data input E, loaded into its register stage when SH/LD is low. |
| 4 | F | input | Serial/parallel data input F, loaded into its register stage when SH/LD is low. |
| 5 | G | input | Serial/parallel data input G, loaded into its register stage when SH/LD is low. |
| 6 | H | input | Serial/parallel data input H, loaded into its register stage when SH/LD is low. |
| 7 | Q H | output | Complementary (inverted) serial output of the register, the inverse of QH. |
| 8 | GND | power_in | Ground reference pin for the device. |
| 9 | QH | output | Serial data output of the shift register, used when the device is clocked. |
| 10 | SER | input | Serial data input to the shift register, shifted in on clocked operation. |
| 11 | A | input | Serial/parallel data input A, loaded into its register stage when SH/LD is low. |
| 12 | B | input | Serial/parallel data input B, loaded into its register stage when SH/LD is low. |
| 13 | C | input | Serial/parallel data input C, loaded into its register stage when SH/LD is low. |
| 14 | D | input | Serial/parallel data input D, loaded into its register stage when SH/LD is low. |
| 15 | CLK INH | input | Clock inhibit input (storage clock inhibit) that disables clocking of the register. |
| 16 | VCC | power_in | Supply pin; the datasheet specifies VCC operation from 2 V to 5.5 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-16 |
| Category | Logic |
| Pins | 16 |
CAD (KiCad official)
- Symbol:
SN74LV165AD - Footprint:
Package_SO:SOIC-16_3.9x9.9mm_P1.27mm - 3D model: SOIC-16 (KiCad packages3D, STEP)
- 3D model files:
sn74lv165ad-etched.step/sn74lv165ad-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);sn74lv165ad.step/sn74lv165ad.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (39 pp, sha256
40785056d9522f8e, retrieved 2026-10-11, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).