# SN74LV161APWR

**Texas Instruments** · Counters, Dividers · TSSOP-16

SN74LV161APWR from Texas Instruments, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | CLR | input | Asynchronous active-low clear that sets all four flip-flop outputs low regardless of CLK, LOAD or enable inputs. |
| 2 | CLK | input | Buffered clock input that triggers the four flip-flops on the rising (positive-going) edge. |
| 3 | A | input | Preset data input A, loaded to QA on the next clock pulse when LOAD is low. |
| 4 | B | input | Preset data input B, loaded to QB on the next clock pulse when LOAD is low. |
| 5 | C | input | Preset data input C, loaded to QC on the next clock pulse when LOAD is low. |
| 6 | D | input | Preset data input D, loaded to QD on the next clock pulse when LOAD is low. |
| 7 | ENP | input | Count-enable input; both ENP and ENT must be high to count, and transitions are allowed regardless of CLK level. |
| 8 | GND | power_in | Ground. |
| 9 | LOAD | input | Synchronous active-low load input that disables counting and presets outputs to A-D data after the next clock pulse. |
| 10 | ENT | input | Count-enable input that must be high to count and is fed forward to enable RCO. |
| 11 | QD | output | Counter output D; drive up to ±12 mA at VCC = 4.5 V to 5.5 V. |
| 12 | QC | output | Counter output C; drive up to ±12 mA at VCC = 4.5 V to 5.5 V. |
| 13 | QB | output | Counter output B; drive up to ±12 mA at VCC = 4.5 V to 5.5 V. |
| 14 | QA | output | Counter output A; drive up to ±12 mA at VCC = 4.5 V to 5.5 V. |
| 15 | RCO | output | Ripple-carry output that produces a high-level pulse at maximum count (9 or 15 with QA high) to enable cascaded stages. |
| 16 | VCC | power_in | Supply voltage, 2 V to 5.5 V recommended operating range (absolute maximum 7 V). |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | TSSOP-16 |
| Category | Logic |
| Pins | 16 |

## CAD (KiCad official)

- Symbol: `SN74LV161APWR`
- Footprint: `Package_SO:TSSOP-16_4.4x5mm_P0.65mm`
- 3D model: TSSOP-16 (KiCad packages3D, STEP)
- 3D model files: `sn74lv161apwr-etched.step` / `sn74lv161apwr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `sn74lv161apwr.step` / `sn74lv161apwr.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/lit/ds/symlink/sn74lv161a.pdf) (28 pp, sha256 `964a83f61a59c69c`, retrieved 2026-10-05, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/sn74lv161apwr-datasheet.pdf)