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Contents

README

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SN74LV138APWR

Texas Instruments · Signal Switches, Multiplexers, Decoders · TSSOP-16

SN74LV138APWR from Texas Instruments, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 A0 input Address select input 0; binary-select input used with A1 and A2 to select one of eight output lines.
2 A1 input Address select input 1; binary-select input used with A0 and A2 to select one of eight output lines.
3 A2 input Address select input 2; binary-select input used with A0 and A1 to select one of eight output lines.
4 G0 input Strobe input, active low; enables decoder when held low with G1 low and G2 high.
5 G1 input Strobe input, active low; enables decoder when held low with G0 low and G2 high.
6 G2 input Strobe input, active high; enables decoder when held high with G0 and G1 low.
7 Y7 output Output 7; active-low decoder output driven low when selected by address inputs and decoder is enabled.
8 GND power_in Ground reference; provides return path for logic signals and supply current.
9 Y6 output Output 6; active-low decoder output driven low when selected by address inputs and decoder is enabled.
10 Y5 output Output 5; active-low decoder output driven low when selected by address inputs and decoder is enabled.
11 Y4 output Output 4; active-low decoder output driven low when selected by address inputs and decoder is enabled.
12 Y3 output Output 3; active-low decoder output driven low when selected by address inputs and decoder is enabled.
13 Y2 output Output 2; active-low decoder output driven low when selected by address inputs and decoder is enabled.
14 Y1 output Output 1; active-low decoder output driven low when selected by address inputs and decoder is enabled.
15 Y0 output Output 0; active-low decoder output driven low when selected by address inputs and decoder is enabled.
16 VCC power_in Positive supply voltage; recommended operating range is 2 V to 5.5 V per Recommended Operating Conditions.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package TSSOP-16
Category Logic
Pins 16

CAD (KiCad official)

  • Symbol: SN74LV138APWR
  • Footprint: Package_SO:TSSOP-16_4.4x5mm_P0.65mm
  • 3D model: TSSOP-16 (KiCad packages3D, STEP)
  • 3D model files: sn74lv138apwr-etched.step / sn74lv138apwr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74lv138apwr.step / sn74lv138apwr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (40 pp, sha256 2c24708519ee350d, retrieved 2026-09-23, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF