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SN74LV123APWR

Public Made by Adom

by adom

Texas Instruments Monostable Multivibrators, TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Generated by kicad-footprint-generator · KiCad file format 20260206
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docs sn74lv123apwr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 3d ago
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package.json Publish 0.1.0 · Ray 4d ago
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README.md Initial commit: component/sn74lv123apwr · Ray 4d ago
sn74lv123apwr-etched.fit.json sn74lv123apwr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 3d ago
sn74lv123apwr-etched.glb sn74lv123apwr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 3d ago
sn74lv123apwr-etched.step sn74lv123apwr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 3d ago
sn74lv123apwr.glb Publish 0.1.0 · Ray 4d ago
sn74lv123apwr.kicad_mod Publish 0.1.0 · Ray 4d ago
sn74lv123apwr.kicad_sym Publish 0.1.0 · Ray 4d ago
sn74lv123apwr.lbr Publish 0.1.0 · Ray 4d ago
sn74lv123apwr.step Publish 0.1.0 · Ray 4d ago

SN74LV123APWR

Texas Instruments · Monostable Multivibrators · TSSOP-16

SN74LV123APWR from Texas Instruments, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1A input Channel 1 falling-edge trigger input when 1B = low; hold low for other input methods.
2 1B input Channel 1 rising-edge trigger input when 1A = high; hold high for other input methods.
3 1CLR input Channel 1 rising-edge trigger when 1A = high and 1B = low; active-low clear input that can cut pulse length short by driving low during output.
4 1Q output Channel 1 inverted output.
5 2Q output Channel 2 output.
6 2Cext passive Channel 2 external timing capacitor negative connection.
7 2Rext/Cext passive Channel 2 external timing capacitor and resistor junction connection.
8 GND power_in Ground connection (0 V reference).
9 2A input Channel 2 falling-edge trigger input when 2B = low; hold low for other input methods.
10 2B input Channel 2 rising-edge trigger input when 2A = high; hold high for other input methods.
11 2CLR input Channel 2 rising-edge trigger when 2A = high and 2B = low; active-low clear input that can cut pulse length short by driving low during output.
12 2Q output Channel 2 inverted output.
13 1Q output Channel 1 output.
14 1Cext passive Channel 1 external timing capacitor negative connection.
15 1Rext/Cext passive Channel 1 external timing capacitor and resistor junction connection.
16 VCC power_in Power supply, 2 V to 5.5 V operating range.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package TSSOP-16
Category Logic
Pins 16

CAD (KiCad official)

  • Symbol: SN74LV123APWR
  • Footprint: Package_SO:TSSOP-16_4.4x5mm_P0.65mm
  • 3D model: TSSOP-16 (KiCad packages3D, STEP)
  • 3D model files: sn74lv123apwr-etched.step / sn74lv123apwr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74lv123apwr.step / sn74lv123apwr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (37 pp, sha256 177536726ba54dee, retrieved 2026-10-01, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF