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SN74LV10APWR

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Texas Instruments Logic Gates, TSSOP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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SN74LV10APWR

Texas Instruments · Logic Gates · TSSOP-14

SN74LV10APWR from Texas Instruments, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1A input Gate 1 input A, with input voltage range 0 V to 5.5 V; unused inputs must be held at VCC or GND.
2 1B input Gate 1 input B, with input voltage range 0 V to 5.5 V; unused inputs must be held at VCC or GND.
3 2A input Gate 2 input A, with input voltage range 0 V to 5.5 V; unused inputs must be held at VCC or GND.
4 2B input Gate 2 input B, with input voltage range 0 V to 5.5 V; unused inputs must be held at VCC or GND.
5 2C input Gate 2 input C, with input voltage range 0 V to 5.5 V; unused inputs must be held at VCC or GND.
6 2Y output Gate 2 NAND output (Y = A•B•C inverted), recommended output current of ±12 mA at VCC = 4.5 V to 5.5 V.
7 GND power_in Ground pin; continuous current through VCC or GND is limited to ±50 mA.
8 3Y output Gate 3 NAND output (Y = A•B•C inverted), recommended output current of ±12 mA at VCC = 4.5 V to 5.5 V.
9 3A input Gate 3 input A, with input voltage range 0 V to 5.5 V; unused inputs must be held at VCC or GND.
10 3B input Gate 3 input B, with input voltage range 0 V to 5.5 V; unused inputs must be held at VCC or GND.
11 3C input Gate 3 input C, with input voltage range 0 V to 5.5 V; unused inputs must be held at VCC or GND.
12 1Y output Gate 1 NAND output (Y = A•B•C inverted), recommended output current of ±12 mA at VCC = 4.5 V to 5.5 V.
13 1C input Gate 1 input C, with input voltage range 0 V to 5.5 V; unused inputs must be held at VCC or GND.
14 VCC power_in Power supply pin, recommended operating range 2 V to 5.5 V, with a 0.1-µF bypass capacitor recommended close to the pin.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package TSSOP-14
Category Logic
Pins 14

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VCC 2 5.5 V 4
High level input voltage VIH 1.5 V VCC = 2 V 4
Low level input voltage VIL 0.5 V VCC = 2 V 4
High level output current IOH -50 µA VCC = 2 V 4
High level output current IOH -2 mA VCC = 2.3 V to 2.7 V 4
High level output current IOH -6 mA VCC = 3 V to 3.6 V 4
High level output current IOH -12 mA VCC = 4.5 V to 5.5 V 4
Low level output current IOL 50 µA VCC = 2 V 5
Low level output current IOL 2 mA VCC = 2.3 V to 2.7 V 5
Low level output current IOL 6 mA VCC = 3 V to 3.6 V 5
Low level output current IOL 12 mA VCC = 4.5 V to 5.5 V 5
Input transition rise and fall rate Δt/Δv 200 ns/V VCC = 2.3 V to 2.7 V 5
Input transition rise and fall rate Δt/Δv 100 ns/V VCC = 3 V to 3.6 V 5
Input transition rise and fall rate Δt/Δv 20 ns/V VCC = 4.5 V to 5.5 V 5
Operating free-air temperature TA -40 85 °C 5
Supply voltage range VCC -0.5 7 V 4
Input voltage range VI -0.5 7 V 4
Output voltage range applied in high or low state VO -0.5 V Limited to 5.5 V maximum 4
Output voltage range applied in power-off state VO -0.5 7 V power-off state 4
Input clamp current IIK -20 mA VI < 0 4
Output clamp current IOK -50 mA VO < 0 4
Continuous output current IO -25 25 mA VO = 0 to VCC 4
Continuous current through VCC or GND -50 50 mA 4
Package thermal impedance θJA 150 °C 4
Storage temperature Tstg -65 150 °C 4
Junction-to-ambient thermal resistance (PW, 14 pins) RθJA 113 °C/W PW package, 14 pins 4
High-level output voltage VOH 2 V IOH = -2 mA, VCC 2.3 V 5
High-level output voltage VOH 2.48 V IOH = -6 mA, VCC 3 V 5
High-level output voltage VOH 3.8 V IOH = -12 mA, VCC 4.5 V 5
Low-level output voltage VOL 0.1 V IOL = 50 µA, VCC 2 V to 5.5 V 5
Low-level output voltage VOL 0.4 V IOL = 2 mA, VCC 2.3 V 5
Low-level output voltage VOL 0.44 V IOL = 6 mA, VCC 3 V 5
Low-level output voltage VOL 0.55 V IOL = 12 mA, VCC 4.5 V 5
Input leakage current II -1 1 µA VI = 5.5 V or GND, VCC 0 to 5.5 V 5
Supply current ICC 20 µA VI = VCC or GND, IO = 0, VCC 5.5 V 5
Input capacitance Ci 1.9 pF VI = VCC or GND, VCC 3.3 V 5
tpd A, B, or C to Y, 25 C, VCC 2.5 V tpd 7.1 13 ns CL = 15 pF, TA = 25°C 5
tpd A, B, or C to Y, full range, VCC 2.5 V tpd 1 15.5 ns CL = 15 pF, full operating range 5
tpd A, B, or C to Y, 25 C, VCC 2.5 V tpd 10.3 17.1 ns CL = 50 pF, TA = 25°C 5
tpd A, B, or C to Y, full range, VCC 2.5 V tpd 1 20.5 ns CL = 50 pF, full operating range 5
tpd A, B, or C to Y, 25 C, VCC 3.3 V tpd 5.2 8.4 ns CL = 15 pF, TA = 25°C 6
tpd A, B, or C to Y, full range, VCC 3.3 V tpd 1 10 ns CL = 15 pF, full operating range 6
tpd A, B, or C to Y, 25 C, VCC 3.3 V tpd 7.4 11.9 ns CL = 50 pF, TA = 25°C 6
tpd A, B, or C to Y, full range, VCC 3.3 V tpd 1 13.5 ns CL = 50 pF, full operating range 6
tpd A, B, or C to Y, 25 C, VCC 5 V tpd 3.9 5.9 ns CL = 15 pF, TA = 25°C 6
tpd A, B, or C to Y, full range, VCC 5 V tpd 1 7 ns CL = 15 pF, full operating range 6
tpd A, B, or C to Y, 25 C, VCC 5 V tpd 5.4 7.9 ns CL = 50 pF, TA = 25°C 6
tpd A, B, or C to Y, full range, VCC 5 V tpd 1 9 ns CL = 50 pF, full operating range 6
Quiet output, maximum dynamic VOL VOL(P) 0.2 0.8 V VCC = 3.3 V, CL = 50 pF, TA = 25°C 6
Quiet output, minimum dynamic VOL VOL(V) 0 -0.8 V VCC = 3.3 V, CL = 50 pF, TA = 25°C 6
Quiet output, minimum dynamic VOH VOH(V) 3.2 V VCC = 3.3 V, CL = 50 pF, TA = 25°C 6
High-level dynamic input voltage VIH(D) 2.31 V VCC = 3.3 V, CL = 50 pF, TA = 25°C 6
Low-level dynamic input voltage VIL(D) 0.99 V VCC = 3.3 V, CL = 50 pF, TA = 25°C 6
Power dissipation capacitance Cpd 14 pF CL = 50 pF, f = 10 MHz, VCC 3.3 V 6
Power dissipation capacitance Cpd 16.7 pF CL = 50 pF, f = 10 MHz, VCC 5 V 6

CAD (KiCad official)

  • Symbol: SN74LV10APWR
  • Footprint: Package_SO:TSSOP-14_4.4x5mm_P0.65mm
  • 3D model: TSSOP-14 (KiCad packages3D, STEP)
  • 3D model files: sn74lv10apwr-etched.step / sn74lv10apwr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74lv10apwr.step / sn74lv10apwr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (22 pp, sha256 e13525015f8a6f8a, retrieved 2026-10-17, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF