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SN74LV00ADR

Texas Instruments · Logic Gates · SOIC-14

SN74LV00ADR from Texas Instruments, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1A input Input A of NAND gate 1; inputs accept up to 5.5 V at any valid VCC (overvoltage tolerant).
2 1B input Input B of NAND gate 1; inputs accept up to 5.5 V at any valid VCC (overvoltage tolerant).
3 1Y output Output of NAND gate 1; load current should not exceed 25 mA per output and 50 mA total for the part.
4 2A input Input A of NAND gate 2; inputs accept up to 5.5 V at any valid VCC (overvoltage tolerant).
5 2B input Input B of NAND gate 2; inputs accept up to 5.5 V at any valid VCC (overvoltage tolerant).
6 2Y output Output of NAND gate 2; load current should not exceed 25 mA per output and 50 mA total for the part.
7 GND power_in Ground reference pin for the device.
8 3Y output Output of NAND gate 3; load current should not exceed 25 mA per output and 50 mA total for the part.
9 3A input Input A of NAND gate 3; inputs accept up to 5.5 V at any valid VCC (overvoltage tolerant).
10 3B input Input B of NAND gate 3; inputs accept up to 5.5 V at any valid VCC (overvoltage tolerant).
11 4Y output Output of NAND gate 4; load current should not exceed 25 mA per output and 50 mA total for the part.
12 4A input Input A of NAND gate 4; inputs accept up to 5.5 V at any valid VCC (overvoltage tolerant).
13 4B input Input B of NAND gate 4; inputs accept up to 5.5 V at any valid VCC (overvoltage tolerant).
14 VCC power_in Supply pin; the recommended operating supply range is 2 V to 5.5 V.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-14
Category Logic
Pins 14

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
High-level output voltage VOH 2 V IOH = -2 mA; VCC = 2.3 V 6
High-level output voltage VOH 2.48 V IOH = -6 mA; VCC = 3 V 6
High-level output voltage VOH 3.8 V IOH = -12 mA; VCC = 4.5 V 6
Low-level output voltage VOL 0.1 V IOL = 50 µA; VCC = 2 V to 5.5 V 6
Low-level output voltage VOL 0.4 V IOL = 2 mA; VCC = 2.3 V 6
Low-level output voltage VOL 0.44 V IOL = 6 mA; VCC = 3 V 6
Low-level output voltage VOL 0.55 V IOL = 12 mA; VCC = 4.5 V 6
Input current II -1 1 µA VI = 5.5 V or GND; VCC = 0 to 5.5 V 6
Supply current ICC 20 µA VI = VCC or GND, IO = 0; VCC = 5.5 V 6
Power-off leakage current Ioff 5 µA VI or VO = 0 to 5.5 V; VCC = 0 6
Propagation delay, A to Y tpd 1 7.1 16 ns CL = 15 pF; VCC = 2.5 V ± 0.2 V; min/max at TA = -40°C to 125°C; typ at TA = 25°C 6
Propagation delay, A to Y tpd 1 9.6 21 ns CL = 50 pF; VCC = 2.5 V ± 0.2 V; min/max at TA = -40°C to 125°C; typ at TA = 25°C 6
Propagation delay, A to Y tpd 1 5 10.5 ns CL = 15 pF; VCC = 3.3 V ± 0.3 V; min/max at TA = -40°C to 125°C; typ at TA = 25°C 6
Propagation delay, A to Y tpd 1 6.9 14 ns CL = 50 pF; VCC = 3.3 V ± 0.3 V; min/max at TA = -40°C to 125°C; typ at TA = 25°C 6
Propagation delay, A to Y tpd 1 3.6 7 ns CL = 15 pF; VCC = 5 V ± 0.5 V; min/max at TA = -40°C to 125°C; typ at TA = 25°C 6
Propagation delay, A to Y tpd 1 4.9 9 ns CL = 50 pF; VCC = 5 V ± 0.5 V; min/max at TA = -40°C to 125°C; typ at TA = 25°C 6
Input capacitance Ci 3.3 pF VI = VCC or GND; VCC = 3.3 V 6
Supply voltage range VCC -0.5 7 V 4
Input voltage range VI -0.5 7 V 4
Voltage range applied to any output in high-impedance or power-off state VO -0.5 7 V 4
Output voltage range VO -0.5 V Maximum printed as VCC + 0.5 V; limited to 5.5 V maximum 4
Input clamp current IIK -20 mA VI < 0 4
Output clamp current IOK -50 mA VO < 0 4
Continuous output current IO -25 25 mA VO = 0 to VCC 4
Continuous current through VCC or GND -50 50 mA 4
Storage temperature range Tstg -65 150 °C 4
Supply voltage VCC 2 5.5 V 5
High-level input voltage VIH 1.5 V VCC = 2 V 5
Low-level input voltage VIL 0.5 V VCC = 2 V 5
Input voltage VI 0 5.5 V 5
Output voltage VO 0 V Maximum printed as VCC 5
High-level output current IOH -50 µA VCC = 2 V 5
High-level output current IOH -2 mA VCC = 2.3 V to 2.7 V 5
High-level output current IOH -6 mA VCC = 3 V to 3.6 V 5
High-level output current IOH -12 mA VCC = 4.5 V to 5.5 V 5
Low-level output current IOL 50 µA VCC = 2 V 5
Low-level output current IOL 2 mA VCC = 2.3 V to 2.7 V 5
Low-level output current IOL 6 mA VCC = 3 V to 3.6 V 5
Low-level output current IOL 12 mA VCC = 4.5 V to 5.5 V 5
Input transition rise or fall rate Δt/Δv 200 ns/V VCC = 2.3 V to 2.7 V 5
Input transition rise or fall rate Δt/Δv 100 ns/V VCC = 3 V to 3.6 V 5
Input transition rise or fall rate Δt/Δv 20 ns/V VCC = 4.5 V to 5.5 V 5
Operating free-air temperature TA -40 125 °C 5
Junction-to-ambient thermal resistance RθJA 90.6 °C/W D package, 14 pins 5
Junction-to-case (top) thermal resistance RθJC(top) 50.9 °C/W D package, 14 pins 5
Junction-to-board thermal resistance RθJB 44.8 °C/W D package, 14 pins 5
Junction-to-top characterization parameter ψJT 14.7 °C/W D package, 14 pins 5
Junction-to-board characterization parameter ψJB 44.5 °C/W D package, 14 pins 5

CAD (KiCad official)

  • Symbol: SN74LV00ADR
  • Footprint: Package_SO:SOIC-14_3.9x8.7mm_P1.27mm
  • 3D model: SOIC-14 (KiCad packages3D, STEP)
  • 3D model files: sn74lv00adr-etched.step / sn74lv00adr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74lv00adr.step / sn74lv00adr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (29 pp, sha256 2f428ff83532785d, retrieved 2026-10-18, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF