component
SN74LS93DR
Public Made by Adomby adom
lingxingic Counters, Dividers, SOP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
main
SN74LS93DR
lingxingic · Counters, Dividers · SOP-14
SN74LS93DR from lingxingic, in a SOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | CP1 | input | Clock input for the 2nd, 3rd and 4th flip-flop sections, edge-triggered on HIGH-to-LOW transitions. |
| 2 | MR1 | input | Asynchronous master reset input, active HIGH; used together with MR2 to clear all outputs Q0 to Q3. |
| 3 | MR2 | input | Asynchronous master reset input, active HIGH; used together with MR1 to clear all outputs Q0 to Q3. |
| 4 | NC | unconnected | Not connected. |
| 5 | VCC | power_in | Supply voltage: recommended 2.0 V to 6.0 V (5.0 V typical); absolute maximum -0.5 V to +7 V. |
| 6 | NC | unconnected | Not connected. |
| 7 | NC | unconnected | Not connected. |
| 8 | Q2 | output | Flip-flop output, bit 2 of the 4-bit binary count. |
| 9 | Q1 | output | Flip-flop output, bit 1 of the 4-bit binary count. |
| 10 | GND | power_in | Ground reference (0 V); all voltages are referenced to this pin. |
| 11 | Q3 | output | Flip-flop output, bit 3 (most significant bit) of the 4-bit binary count. |
| 12 | Q0 | output | Flip-flop output, bit 0 (least significant bit) of the 4-bit binary count; datasheet notes it is connected to CP1 externally for binary ripple counting. |
| 13 | NC | unconnected | Not connected. |
| 14 | CP0 | input | Clock input for the 1st flip-flop section, edge-triggered on HIGH-to-LOW transitions. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | lingxingic |
| Package | SOP-14 |
| Category | Logic |
| Pins | 14 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| supply voltage | VCC | 2 | 5 | 6 | V | 7 | |
| input voltage | VI | 0 | V | 7 | |||
| output voltage | VO | 0 | V | 7 | |||
| ambient temperature | Tamb | -40 | 125 | ℃ | 7 | ||
| supply voltage | VCC | -0.5 | 7 | V | 7 | ||
| supply current | ICC | 50 | mA | 7 | |||
| ground current | IGND | -50 | mA | 7 | |||
| input clamping current | IIK | -20 | 20 | mA | VI < -0.5V or VI > VCC+0.5V | 7 | |
| output clamping current | IOK | -20 | 20 | mA | VO < -0.5V or VO > VCC+0.5V | 7 | |
| output current | IO | -25 | 25 | mA | -0.5V < VO < VCC+0.5V | 7 | |
| storage temperature | Tstg | -65 | 150 | ℃ | 7 | ||
| soldering temperature | TL | 260 | ℃ | 10s, SOP/TSSOP | 7 | ||
| HIGH-level input voltage | VIH | 1.5 | 1.2 | V | VCC=2.0V; Tamb=-40 to +85℃ | 8 | |
| HIGH-level input voltage | VIH | 3.15 | 2.4 | V | VCC=4.5V; Tamb=-40 to +85℃ | 8 | |
| HIGH-level input voltage | VIH | 4.2 | 3.2 | V | VCC=6.0V; Tamb=-40 to +85℃ | 8 | |
| LOW-level input voltage | VIL | 0.8 | 0.5 | V | VCC=2.0V; Tamb=-40 to +85℃ | 8 | |
| LOW-level input voltage | VIL | 2.1 | 1.35 | V | VCC=4.5V; Tamb=-40 to +85℃ | 8 | |
| LOW-level input voltage | VIL | 2.8 | 1.8 | V | VCC=6.0V; Tamb=-40 to +85℃ | 8 | |
| HIGH-level output voltage | VOH | 1.9 | 2 | V | VCC=2.0V; IO=-20uA; Tamb=-40 to +85℃ | 8 | |
| HIGH-level output voltage | VOH | 4.4 | 4.5 | V | VCC=4.5V; IO=-20uA; Tamb=-40 to +85℃ | 8 | |
| HIGH-level output voltage | VOH | 5.9 | 6 | V | VCC=6.0V; IO=-20uA; Tamb=-40 to +85℃ | 8 | |
| HIGH-level output voltage | VOH | 3.84 | 4.32 | V | VCC=4.5V; IO=-4.0mA; Tamb=-40 to +85℃ | 8 | |
| HIGH-level output voltage | VOH | 5.34 | 5.81 | V | VCC=6.0V; IO=-5.2mA; Tamb=-40 to +85℃ | 8 | |
| LOW-level output voltage | VOL | 0 | 0.1 | V | VCC=2.0V; IO=20uA; Tamb=-40 to +85℃ | 8 | |
| LOW-level output voltage | VOL | 0.15 | 0.33 | V | VCC=4.5V; IO=4.0mA; Tamb=-40 to +85℃ | 8 | |
| LOW-level output voltage | VOL | 0.16 | 0.33 | V | VCC=6.0V; IO=5.2mA; Tamb=-40 to +85℃ | 8 | |
| input leakage current | II | -1 | 1 | uA | VCC=6.0V; VI=VCC or GND; Tamb=-40 to +85℃ | 8 | |
| supply current | ICC | 80 | uA | VCC=6.0V; VI=VCC or GND; IO=0A; Tamb=-40 to +85℃ | 8 | ||
| HIGH-level input voltage | VIH | 1.5 | V | VCC=2.0V; Tamb=-40 to +125℃ | 9 | ||
| HIGH-level input voltage | VIH | 3.15 | V | VCC=4.5V; Tamb=-40 to +125℃ | 9 | ||
| HIGH-level input voltage | VIH | 4.2 | V | VCC=6.0V; Tamb=-40 to +125℃ | 9 | ||
| LOW-level input voltage | VIL | 0.5 | V | VCC=2.0V; Tamb=-40 to +125℃ | 9 | ||
| LOW-level input voltage | VIL | 1.35 | V | VCC=4.5V; Tamb=-40 to +125℃ | 9 | ||
| LOW-level input voltage | VIL | 1.8 | V | VCC=6.0V; Tamb=-40 to +125℃ | 9 | ||
| HIGH-level output voltage | VOH | 1.9 | V | VCC=2.0V; IO=-20uA; Tamb=-40 to +125℃ | 9 | ||
| HIGH-level output voltage | VOH | 4.4 | V | VCC=4.5V; IO=-20uA; Tamb=-40 to +125℃ | 9 | ||
| HIGH-level output voltage | VOH | 5.9 | V | VCC=6.0V; IO=-20uA; Tamb=-40 to +125℃ | 9 | ||
| HIGH-level output voltage | VOH | 3.7 | V | VCC=4.5V; IO=-4.0mA; Tamb=-40 to +125℃ | 9 | ||
| HIGH-level output voltage | VOH | 5.2 | V | VCC=6.0V; IO=-5.2mA; Tamb=-40 to +125℃ | 9 | ||
| LOW-level output voltage | VOL | 0.1 | V | VCC=2.0V; IO=20uA; Tamb=-40 to +125℃ | 9 | ||
| LOW-level output voltage | VOL | 0.4 | V | VCC=4.5V; IO=4.0mA; Tamb=-40 to +125℃ | 9 | ||
| input leakage current | II | -1 | 1 | uA | VCC=6.0V; VI=VCC or GND; Tamb=-40 to +125℃ | 9 | |
| supply current | ICC | 160 | uA | VCC=6.0V; VI=VCC or GND; IO=0A; Tamb=-40 to +125℃ | 9 | ||
| maximum clock frequency | fmax | 4.8 | 30 | MHz | VCC=2.0V; CL=50pF; see Figure 4; Tamb=-40 to +85℃ | 10 | |
| maximum clock frequency | fmax | 24 | 91 | MHz | VCC=4.5V; CL=50pF; Tamb=-40 to +85℃ | 10 | |
| maximum clock frequency | fmax | 28 | 108 | MHz | VCC=6.0V; CL=50pF; Tamb=-40 to +85℃ | 10 | |
| CP0 to Q0 propagation delay | tPLH, tPHL | 41 | 155 | ns | VCC=2.0V; CL=50pF; see Figure 4; Tamb=-40 to +85℃ | 10 | |
| CP0 to Q0 propagation delay | tPLH, tPHL | 15 | 31 | ns | VCC=4.5V; CL=50pF; Tamb=-40 to +85℃ | 10 | |
| CP0 to Q0 propagation delay | tPLH, tPHL | 12 | 26 | ns | VCC=6.0V; CL=50pF; Tamb=-40 to +85℃ | 10 | |
| CP0 to Q0 propagation delay | tPLH, tPHL | 190 | ns | VCC=2.0V; CL=50pF; see Figure 4; Tamb=-40 to +125℃ | 11 | ||
| CP0 to Q0 propagation delay | tPLH, tPHL | 38 | ns | VCC=4.5V; CL=50pF; Tamb=-40 to +125℃ | 11 | ||
| CP0 to Q0 propagation delay | tPLH, tPHL | 32 | ns | VCC=6.0V; CL=50pF; Tamb=-40 to +125℃ | 11 | ||
| maximum clock frequency | fmax | 4 | MHz | VCC=2.0V; CL=50pF; see Figure 4; Tamb=-40 to +125℃ | 11 | ||
| maximum clock frequency | fmax | 20 | MHz | VCC=4.5V; CL=50pF; Tamb=-40 to +125℃ | 11 | ||
| maximum clock frequency | fmax | 24 | MHz | VCC=6.0V; CL=50pF; Tamb=-40 to +125℃ | 11 |
CAD (KiCad official)
- Symbol:
SN74LS93DR - Footprint:
Package_SO:SOIC-14_3.9x8.7mm_P1.27mm - 3D model: SOP-14 (KiCad packages3D, STEP)
- 3D model files:
sn74ls93dr-etched.step/sn74ls93dr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);sn74ls93dr.step/sn74ls93dr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: lingxingic datasheet (17 pp, sha256
9c97eb5e85e0c43a, retrieved 2026-10-18, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# SN74LS93DR
**lingxingic** · Counters, Dividers · SOP-14
SN74LS93DR from lingxingic, in a SOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | CP1 | input | Clock input for the 2nd, 3rd and 4th flip-flop sections, edge-triggered on HIGH-to-LOW transitions. |
| 2 | MR1 | input | Asynchronous master reset input, active HIGH; used together with MR2 to clear all outputs Q0 to Q3. |
| 3 | MR2 | input | Asynchronous master reset input, active HIGH; used together with MR1 to clear all outputs Q0 to Q3. |
| 4 | NC | unconnected | Not connected. |
| 5 | VCC | power_in | Supply voltage: recommended 2.0 V to 6.0 V (5.0 V typical); absolute maximum -0.5 V to +7 V. |
| 6 | NC | unconnected | Not connected. |
| 7 | NC | unconnected | Not connected. |
| 8 | Q2 | output | Flip-flop output, bit 2 of the 4-bit binary count. |
| 9 | Q1 | output | Flip-flop output, bit 1 of the 4-bit binary count. |
| 10 | GND | power_in | Ground reference (0 V); all voltages are referenced to this pin. |
| 11 | Q3 | output | Flip-flop output, bit 3 (most significant bit) of the 4-bit binary count. |
| 12 | Q0 | output | Flip-flop output, bit 0 (least significant bit) of the 4-bit binary count; datasheet notes it is connected to CP1 externally for binary ripple counting. |
| 13 | NC | unconnected | Not connected. |
| 14 | CP0 | input | Clock input for the 1st flip-flop section, edge-triggered on HIGH-to-LOW transitions. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | lingxingic |
| Package | SOP-14 |
| Category | Logic |
| Pins | 14 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| supply voltage | VCC | 2 | 5 | 6 | V | | 7 |
| input voltage | VI | 0 | | | V | | 7 |
| output voltage | VO | 0 | | | V | | 7 |
| ambient temperature | Tamb | -40 | | 125 | ℃ | | 7 |
| supply voltage | VCC | -0.5 | | 7 | V | | 7 |
| supply current | ICC | | | 50 | mA | | 7 |
| ground current | IGND | -50 | | | mA | | 7 |
| input clamping current | IIK | -20 | | 20 | mA | VI < -0.5V or VI > VCC+0.5V | 7 |
| output clamping current | IOK | -20 | | 20 | mA | VO < -0.5V or VO > VCC+0.5V | 7 |
| output current | IO | -25 | | 25 | mA | -0.5V < VO < VCC+0.5V | 7 |
| storage temperature | Tstg | -65 | | 150 | ℃ | | 7 |
| soldering temperature | TL | | | 260 | ℃ | 10s, SOP/TSSOP | 7 |
| HIGH-level input voltage | VIH | 1.5 | 1.2 | | V | VCC=2.0V; Tamb=-40 to +85℃ | 8 |
| HIGH-level input voltage | VIH | 3.15 | 2.4 | | V | VCC=4.5V; Tamb=-40 to +85℃ | 8 |
| HIGH-level input voltage | VIH | 4.2 | 3.2 | | V | VCC=6.0V; Tamb=-40 to +85℃ | 8 |
| LOW-level input voltage | VIL | | 0.8 | 0.5 | V | VCC=2.0V; Tamb=-40 to +85℃ | 8 |
| LOW-level input voltage | VIL | | 2.1 | 1.35 | V | VCC=4.5V; Tamb=-40 to +85℃ | 8 |
| LOW-level input voltage | VIL | | 2.8 | 1.8 | V | VCC=6.0V; Tamb=-40 to +85℃ | 8 |
| HIGH-level output voltage | VOH | 1.9 | 2 | | V | VCC=2.0V; IO=-20uA; Tamb=-40 to +85℃ | 8 |
| HIGH-level output voltage | VOH | 4.4 | 4.5 | | V | VCC=4.5V; IO=-20uA; Tamb=-40 to +85℃ | 8 |
| HIGH-level output voltage | VOH | 5.9 | 6 | | V | VCC=6.0V; IO=-20uA; Tamb=-40 to +85℃ | 8 |
| HIGH-level output voltage | VOH | 3.84 | 4.32 | | V | VCC=4.5V; IO=-4.0mA; Tamb=-40 to +85℃ | 8 |
| HIGH-level output voltage | VOH | 5.34 | 5.81 | | V | VCC=6.0V; IO=-5.2mA; Tamb=-40 to +85℃ | 8 |
| LOW-level output voltage | VOL | | 0 | 0.1 | V | VCC=2.0V; IO=20uA; Tamb=-40 to +85℃ | 8 |
| LOW-level output voltage | VOL | | 0.15 | 0.33 | V | VCC=4.5V; IO=4.0mA; Tamb=-40 to +85℃ | 8 |
| LOW-level output voltage | VOL | | 0.16 | 0.33 | V | VCC=6.0V; IO=5.2mA; Tamb=-40 to +85℃ | 8 |
| input leakage current | II | -1 | | 1 | uA | VCC=6.0V; VI=VCC or GND; Tamb=-40 to +85℃ | 8 |
| supply current | ICC | | | 80 | uA | VCC=6.0V; VI=VCC or GND; IO=0A; Tamb=-40 to +85℃ | 8 |
| HIGH-level input voltage | VIH | 1.5 | | | V | VCC=2.0V; Tamb=-40 to +125℃ | 9 |
| HIGH-level input voltage | VIH | 3.15 | | | V | VCC=4.5V; Tamb=-40 to +125℃ | 9 |
| HIGH-level input voltage | VIH | 4.2 | | | V | VCC=6.0V; Tamb=-40 to +125℃ | 9 |
| LOW-level input voltage | VIL | | | 0.5 | V | VCC=2.0V; Tamb=-40 to +125℃ | 9 |
| LOW-level input voltage | VIL | | | 1.35 | V | VCC=4.5V; Tamb=-40 to +125℃ | 9 |
| LOW-level input voltage | VIL | | | 1.8 | V | VCC=6.0V; Tamb=-40 to +125℃ | 9 |
| HIGH-level output voltage | VOH | 1.9 | | | V | VCC=2.0V; IO=-20uA; Tamb=-40 to +125℃ | 9 |
| HIGH-level output voltage | VOH | 4.4 | | | V | VCC=4.5V; IO=-20uA; Tamb=-40 to +125℃ | 9 |
| HIGH-level output voltage | VOH | 5.9 | | | V | VCC=6.0V; IO=-20uA; Tamb=-40 to +125℃ | 9 |
| HIGH-level output voltage | VOH | 3.7 | | | V | VCC=4.5V; IO=-4.0mA; Tamb=-40 to +125℃ | 9 |
| HIGH-level output voltage | VOH | 5.2 | | | V | VCC=6.0V; IO=-5.2mA; Tamb=-40 to +125℃ | 9 |
| LOW-level output voltage | VOL | | | 0.1 | V | VCC=2.0V; IO=20uA; Tamb=-40 to +125℃ | 9 |
| LOW-level output voltage | VOL | | | 0.4 | V | VCC=4.5V; IO=4.0mA; Tamb=-40 to +125℃ | 9 |
| input leakage current | II | -1 | | 1 | uA | VCC=6.0V; VI=VCC or GND; Tamb=-40 to +125℃ | 9 |
| supply current | ICC | | | 160 | uA | VCC=6.0V; VI=VCC or GND; IO=0A; Tamb=-40 to +125℃ | 9 |
| maximum clock frequency | fmax | 4.8 | 30 | | MHz | VCC=2.0V; CL=50pF; see Figure 4; Tamb=-40 to +85℃ | 10 |
| maximum clock frequency | fmax | 24 | 91 | | MHz | VCC=4.5V; CL=50pF; Tamb=-40 to +85℃ | 10 |
| maximum clock frequency | fmax | 28 | 108 | | MHz | VCC=6.0V; CL=50pF; Tamb=-40 to +85℃ | 10 |
| CP0 to Q0 propagation delay | tPLH, tPHL | | 41 | 155 | ns | VCC=2.0V; CL=50pF; see Figure 4; Tamb=-40 to +85℃ | 10 |
| CP0 to Q0 propagation delay | tPLH, tPHL | | 15 | 31 | ns | VCC=4.5V; CL=50pF; Tamb=-40 to +85℃ | 10 |
| CP0 to Q0 propagation delay | tPLH, tPHL | | 12 | 26 | ns | VCC=6.0V; CL=50pF; Tamb=-40 to +85℃ | 10 |
| CP0 to Q0 propagation delay | tPLH, tPHL | | | 190 | ns | VCC=2.0V; CL=50pF; see Figure 4; Tamb=-40 to +125℃ | 11 |
| CP0 to Q0 propagation delay | tPLH, tPHL | | | 38 | ns | VCC=4.5V; CL=50pF; Tamb=-40 to +125℃ | 11 |
| CP0 to Q0 propagation delay | tPLH, tPHL | | | 32 | ns | VCC=6.0V; CL=50pF; Tamb=-40 to +125℃ | 11 |
| maximum clock frequency | fmax | 4 | | | MHz | VCC=2.0V; CL=50pF; see Figure 4; Tamb=-40 to +125℃ | 11 |
| maximum clock frequency | fmax | 20 | | | MHz | VCC=4.5V; CL=50pF; Tamb=-40 to +125℃ | 11 |
| maximum clock frequency | fmax | 24 | | | MHz | VCC=6.0V; CL=50pF; Tamb=-40 to +125℃ | 11 |
## CAD (KiCad official)
- Symbol: `SN74LS93DR`
- Footprint: `Package_SO:SOIC-14_3.9x8.7mm_P1.27mm`
- 3D model: SOP-14 (KiCad packages3D, STEP)
- 3D model files: `sn74ls93dr-etched.step` / `sn74ls93dr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `sn74ls93dr.step` / `sn74ls93dr.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [lingxingic datasheet](docs/sn74ls93dr-datasheet.pdf) (17 pp, sha256 `9c97eb5e85e0c43a`, retrieved 2026-10-18, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/sn74ls93dr-datasheet.pdf)