# SN74LS74DR

**lingxingic** · Flip Flops · SOP-14

SN74LS74DR from lingxingic, in a SOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1RD | input | Asynchronous reset input of flip-flop 1, active low. |
| 2 | 1D | input | Data input of flip-flop 1. |
| 3 | 1CP | input | Clock input of flip-flop 1, edge-triggered on the low-to-high transition. |
| 4 | 1SD | input | Asynchronous set input of flip-flop 1, active low. |
| 5 | 1Q | output | True output of flip-flop 1. |
| 6 | 1Q̅ | output | Complementary (inverted) output of flip-flop 1. |
| 7 | GND | power_in | Ground (0 V). |
| 8 | 2Q̅ | output | Complementary (inverted) output of flip-flop 2. |
| 9 | 2Q | output | True output of flip-flop 2. |
| 10 | 2SD | input | Asynchronous set input of flip-flop 2, active low. |
| 11 | 2CP | input | Clock input of flip-flop 2, edge-triggered on the low-to-high transition. |
| 12 | 2D | input | Data input of flip-flop 2. |
| 13 | 2RD | input | Asynchronous reset input of flip-flop 2, active low. |
| 14 | VCC | power_in | Supply voltage, recommended 2.0 V to 6.0 V (absolute maximum 7 V). |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | lingxingic |
| Package | SOP-14 |
| Category | Logic |
| Pins | 14 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage | VCC | -0.5 |  | 7 | V | Tamb=25°C | 8 |
| Input clamp current | IIK | -20 |  | 20 | mA | VI<-0.5V or VI>VCC+0.5V | 8 |
| Output clamp current | IOK | -20 |  | 20 | mA | VO<-0.5V or VO>VCC+0.5V | 8 |
| Output current | IO | -25 |  | 25 | mA | -0.5V<VO<VCC+0.5V | 8 |
| Supply current | ICC |  |  | 100 | mA |  | 8 |
| Ground current | IGND | -100 |  |  | mA |  | 8 |
| Total power dissipation | Ptot |  |  | 500 | mW |  | 8 |
| Storage temperature | Tstg | -65 |  | 150 | °C |  | 8 |
| Soldering temperature SOP/TSSOP | TL |  |  | 260 | °C | 10 s, SOP/TSSOP | 8 |
| Supply voltage | VCC | 2 | 5 | 6 | V |  | 8 |
| Input voltage | VI | 0 |  |  | V | max = VCC | 8 |
| Output voltage | VO | 0 |  |  | V | max = VCC | 8 |
| Input rise and fall slew rate | Δt/ΔV |  |  | 625 | ns/V | VCC=2.0V | 8 |
| Input rise and fall slew rate | Δt/ΔV |  | 1.67 | 139 | ns/V | VCC=4.5V | 8 |
| Input rise and fall slew rate | Δt/ΔV |  |  | 83 | ns/V | VCC=6.0V | 8 |
| Operating ambient temperature | Tamb | -40 |  | 125 | °C |  | 8 |
| High-level input voltage | VIH | 1.5 |  |  | V | VCC=2.0V; Tamb=-40~+125°C | 10 |
| High-level input voltage | VIH | 3.15 |  |  | V | VCC=4.5V; Tamb=-40~+125°C | 10 |
| High-level input voltage | VIH | 4.2 |  |  | V | VCC=6.0V; Tamb=-40~+125°C | 10 |
| Low-level input voltage | VIL |  |  | 0.5 | V | VCC=2.0V; Tamb=-40~+125°C | 10 |
| Low-level input voltage | VIL |  |  | 1.35 | V | VCC=4.5V; Tamb=-40~+125°C | 10 |
| Low-level input voltage | VIL |  |  | 1.8 | V | VCC=6.0V; Tamb=-40~+125°C | 10 |
| High-level output voltage | VOH | 3.7 |  |  | V | VI=VIH或VIL; IO=-4.0mA; VCC=4.5V; Tamb=-40~+125°C | 10 |
| High-level output voltage | VOH | 5.2 |  |  | V | VI=VIH或VIL; IO=-5.2mA; VCC=6.0V; Tamb=-40~+125°C | 10 |
| Low-level output voltage | VOL |  |  | 0.4 | V | VI=VIH或VIL; IO=4.0mA; VCC=4.5V; Tamb=-40~+125°C | 10 |
| Input leakage current | II | -1 |  | 1 | uA | VI=VCC或GND; VCC=6.0V | 10 |
| Quiescent supply current | ICC |  |  | 80 | uA | VI=VCC或GND; IO=0A; VCC=6.0V; Tamb=-40~+125°C | 10 |
| High-level output voltage | VOH | 3.84 | 4.32 |  | V | VI=VIH或VIL; IO=-4.0mA; VCC=4.5V; Tamb=-40~+85°C | 9 |
| High-level output voltage | VOH | 5.34 | 5.81 |  | V | VI=VIH或VIL; IO=-5.2mA; VCC=6.0V; Tamb=-40~+85°C | 9 |
| Low-level output voltage | VOL |  | 0.15 | 0.33 | V | VI=VIH或VIL; IO=4.0mA; VCC=4.5V; Tamb=-40~+85°C | 9 |
| Low-level output voltage | VOL |  | 0.16 | 0.33 | V | VI=VIH或VIL; IO=5.2mA; VCC=6.0V; Tamb=-40~+85°C | 9 |
| Quiescent supply current | ICC |  |  | 40 | uA | VI=VCC或GND; IO=0A; VCC=6.0V; Tamb=-40~+85°C | 9 |
| Input capacitance | CI |  | 3.5 |  | pF | Tamb=-40~+85°C | 9 |
| Propagation delay nCP to nQ, nQ̄ | tpd |  |  | 265 | ns | VCC=2.0V; Tamb=-40~+125°C | 13 |
| Propagation delay nCP to nQ, nQ̄ | tpd |  |  | 53 | ns | VCC=4.5V; Tamb=-40~+125°C | 13 |
| Propagation delay nCP to nQ, nQ̄ | tpd |  |  | 45 | ns | VCC=6.0V; Tamb=-40~+125°C | 13 |
| Propagation delay nSD to nQ, nQ̄ | tpd |  |  | 60 | ns | VCC=4.5V; Tamb=-40~+125°C | 13 |
| Propagation delay nRD to nQ, nQ̄ | tpd |  |  | 60 | ns | VCC=4.5V; Tamb=-40~+125°C | 13 |
| Output transition time | tt |  |  | 22 | ns | VCC=4.5V; Tamb=-40~+125°C | 13 |
| CP pulse width | tW | 24 |  |  | ns | VCC=4.5V; Tamb=-40~+125°C | 13 |
| nSD, nRD pulse width | tW | 24 |  |  | ns | VCC=4.5V; Tamb=-40~+125°C | 13 |
| nSD, nRD recovery time | trec | 9 |  |  | ns | VCC=4.5V; Tamb=-40~+125°C | 13 |
| nD to nCP setup time | tsu | 18 |  |  | ns | VCC=4.5V; Tamb=-40~+125°C | 13 |
| nD to nCP hold time | th | 3 |  |  | ns | VCC=4.5V; Tamb=-40~+125°C | 13 |
| nCP maximum frequency | fmax | 20 |  |  | MHz | VCC=4.5V; Tamb=-40~+125°C | 13 |
| Propagation delay nCP to nQ, nQ̄ | tpd |  | 17 | 44 | ns | VCC=4.5V; Tamb=-40~+85°C | 11 |
| Propagation delay nSD to nQ, nQ̄ | tpd |  | 18 | 50 | ns | VCC=4.5V; Tamb=-40~+85°C | 11 |
| Propagation delay nRD to nQ, nQ̄ | tpd |  | 19 | 50 | ns | VCC=4.5V; Tamb=-40~+85°C | 11 |
| Output transition time | tt |  | 7 | 19 | ns | VCC=4.5V; Tamb=-40~+85°C | 11 |
| CP pulse width | tW | 20 | 7 |  | ns | VCC=4.5V; Tamb=-40~+85°C | 11 |
| nSD, nRD pulse width | tW | 20 | 7 |  | ns | VCC=4.5V; Tamb=-40~+85°C | 11 |
| nSD, nRD recovery time | trec | 8 | 1 |  | ns | VCC=4.5V; Tamb=-40~+85°C | 11 |
| nD to nCP setup time | tsu | 15 | 2 |  | ns | VCC=4.5V; Tamb=-40~+85°C | 11 |
| nD to nCP hold time | th | 3 | -2 |  | ns | VCC=4.5V; Tamb=-40~+85°C | 11 |
| nCP maximum frequency | fmax | 24 | 69 |  | MHz | VCC=4.5V; Tamb=-40~+85°C | 11 |
| Power dissipation capacitance | CPD |  | 24 |  | pF | CL=50pF; f=1MHz; VI=GND~VCC | 11 |

## CAD (KiCad official)

- Symbol: `SN74LS74DR`
- Footprint: `Package_SO:SOIC-14_3.9x8.7mm_P1.27mm`
- 3D model: SOP-14 (KiCad packages3D, STEP)
- 3D model files: `sn74ls74dr-etched.step` / `sn74ls74dr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `sn74ls74dr.step` / `sn74ls74dr.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [lingxingic datasheet](docs/sn74ls74dr-datasheet.pdf) (20 pp, sha256 `3b7790b104e063fb`, retrieved 2026-10-23, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/sn74ls74dr-datasheet.pdf)