# SN74LS645-1N

**Texas Instruments** · Buffers / Drivers · PDIP-20

SN74LS645-1N from Texas Instruments, in a PDIP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | DIR | input | Direction control input: high transmits A data to the B bus, low transmits B data to the A bus (when G is low). |
| 2 | A1 | bidirectional | A-bus I/O 1 with 3-state output and hysteresis at the bus input. |
| 3 | A2 | bidirectional | A-bus I/O 2 with 3-state output and hysteresis at the bus input. |
| 4 | A3 | bidirectional | A-bus I/O 3 with 3-state output and hysteresis at the bus input. |
| 5 | A4 | bidirectional | A-bus I/O 4 with 3-state output and hysteresis at the bus input. |
| 6 | A5 | bidirectional | A-bus I/O 5 with 3-state output and hysteresis at the bus input. |
| 7 | A6 | bidirectional | A-bus I/O 6 with 3-state output and hysteresis at the bus input. |
| 8 | A7 | bidirectional | A-bus I/O 7 with 3-state output and hysteresis at the bus input. |
| 9 | A8 | bidirectional | A-bus I/O 8 with 3-state output and hysteresis at the bus input. |
| 10 | GND | power_in | Ground. |
| 11 | B8 | bidirectional | B-bus I/O 8 with 3-state output and hysteresis at the bus input. |
| 12 | B7 | bidirectional | B-bus I/O 7 with 3-state output and hysteresis at the bus input. |
| 13 | B6 | bidirectional | B-bus I/O 6 with 3-state output and hysteresis at the bus input. |
| 14 | B5 | bidirectional | B-bus I/O 5 with 3-state output and hysteresis at the bus input. |
| 15 | B4 | bidirectional | B-bus I/O 4 with 3-state output and hysteresis at the bus input. |
| 16 | B3 | bidirectional | B-bus I/O 3 with 3-state output and hysteresis at the bus input. |
| 17 | B2 | bidirectional | B-bus I/O 2 with 3-state output and hysteresis at the bus input. |
| 18 | B1 | bidirectional | B-bus I/O 1 with 3-state output and hysteresis at the bus input. |
| 19 | G | input | Active-low enable input; high disables the device so the buses are effectively isolated. |
| 20 | VCC | power_in | Positive supply voltage. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | PDIP-20 |
| Category | Logic ICs |
| Pins | 20 |

## CAD (KiCad official)

- Symbol: `SN74LS645-1N`
- Footprint: `Package_DIP:DIP-20_W7.62mm`
- 3D model: PDIP-20 (KiCad packages3D, STEP)
- 3D model files: `sn74ls645-1n-etched.step` / `sn74ls645-1n-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `sn74ls645-1n.step` / `sn74ls645-1n.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/lit/ds/symlink/sn74ls645-1n.pdf) (21 pp, sha256 `26e250f139497751`, retrieved 2026-10-27, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text+vision), consensus `claude-opus-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/sn74ls645-1n-datasheet.pdf)