component

SN74LS595N

Public Made by Adom

by adom

XBLW Shift Registers, DIP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentlogicsn74ls595nfactory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity

3D Model

Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.

Symbol & Footprint

Schematic Symbol

Open full view ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.

PCB Footprint

Open full view ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.

Datasheet

Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.
Download PDF
Contents

README

markdown

SN74LS595N

XBLW · Shift Registers · DIP-16

SN74LS595N from XBLW, in a DIP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 Q1 tri_state Parallel data output 1 (3-state, high-impedance when OE is HIGH).
2 Q2 tri_state Parallel data output 2 (3-state, high-impedance when OE is HIGH).
3 Q3 tri_state Parallel data output 3 (3-state, high-impedance when OE is HIGH).
4 Q4 tri_state Parallel data output 4 (3-state, high-impedance when OE is HIGH).
5 Q5 tri_state Parallel data output 5 (3-state, high-impedance when OE is HIGH).
6 Q6 tri_state Parallel data output 6 (3-state, high-impedance when OE is HIGH).
7 Q7 tri_state Parallel data output 7 (3-state, high-impedance when OE is HIGH).
8 GND power_in Ground (0 V).
9 Q7S output Serial data output for cascading.
10 MR input Master reset, active LOW; a LOW resets the shift register asynchronously.
11 SHCP input Shift register clock input; data shifts on LOW-to-HIGH transitions.
12 STCP input Storage register clock input; shift register data is transferred to storage on LOW-to-HIGH transition.
13 OE input Output enable input, active LOW; HIGH puts the outputs in high-impedance OFF-state.
14 DS input Serial data input.
15 Q0 tri_state Parallel data output 0 (3-state, high-impedance when OE is HIGH).
16 VCC power_in Supply voltage.

Key specifications

Parameter Value
Manufacturer XBLW
Package DIP-16
Category Logic
Pins 16

CAD (KiCad official)

  • Symbol: SN74LS595N
  • Footprint: Package_DIP:DIP-16_W7.62mm
  • 3D model: DIP-16 (KiCad packages3D, STEP)
  • 3D model files: sn74ls595n-etched.step / sn74ls595n-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74ls595n.step / sn74ls595n.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: XBLW datasheet (17 pp, sha256 1ad5ae59fa1e1c62, retrieved 2026-10-16, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF