component
SN74LS573N
Public Made by Adomby adom
XBLW Latches, DIP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownSN74LS573N
XBLW · Latches · DIP-20
SN74LS573N from XBLW, in a DIP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | OE | input | 3-state output enable input (active LOW); a HIGH forces Q0 to Q7 into the high-impedance OFF-state without changing the latch contents. |
| 2 | D0 | input | Data input to latch 0; inputs include clamp diodes so current-limiting resistors can interface them to voltages above VCC. |
| 3 | D1 | input | Data input to latch 1; inputs include clamp diodes so current-limiting resistors can interface them to voltages above VCC. |
| 4 | D2 | input | Data input to latch 2; inputs include clamp diodes so current-limiting resistors can interface them to voltages above VCC. |
| 5 | D3 | input | Data input to latch 3; inputs include clamp diodes so current-limiting resistors can interface them to voltages above VCC. |
| 6 | D4 | input | Data input to latch 4; inputs include clamp diodes so current-limiting resistors can interface them to voltages above VCC. |
| 7 | D5 | input | Data input to latch 5; inputs include clamp diodes so current-limiting resistors can interface them to voltages above VCC. |
| 8 | D6 | input | Data input to latch 6; inputs include clamp diodes so current-limiting resistors can interface them to voltages above VCC. |
| 9 | D7 | input | Data input to latch 7; inputs include clamp diodes so current-limiting resistors can interface them to voltages above VCC. |
| 10 | GND | power_in | Ground (0 V) reference for the device. |
| 11 | LE | input | Latch enable input (active HIGH); when HIGH the latches are transparent to the D inputs, and when LOW they store the data present at the inputs. |
| 12 | Q7 | tri_state | 3-state non-inverting latch output 7, high-impedance when OE is HIGH. |
| 13 | Q6 | tri_state | 3-state non-inverting latch output 6, high-impedance when OE is HIGH. |
| 14 | Q5 | tri_state | 3-state non-inverting latch output 5, high-impedance when OE is HIGH. |
| 15 | Q4 | tri_state | 3-state non-inverting latch output 4, high-impedance when OE is HIGH. |
| 16 | Q3 | tri_state | 3-state non-inverting latch output 3, high-impedance when OE is HIGH. |
| 17 | Q2 | tri_state | 3-state non-inverting latch output 2, high-impedance when OE is HIGH. |
| 18 | Q1 | tri_state | 3-state non-inverting latch output 1, high-impedance when OE is HIGH. |
| 19 | Q0 | tri_state | 3-state non-inverting latch output 0, high-impedance when OE is HIGH. |
| 20 | VCC | power_in | Supply voltage; recommended range 2.0 V to 6.0 V (typ. 5.0 V), absolute maximum 7.0 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | XBLW |
| Package | DIP-20 |
| Category | Logic |
| Pins | 20 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage | VCC | -0.5 | 7 | V | 6 | ||
| Input clamping current | IIK | -20 | 20 | mA | VI < -0.5V or VI > VCC+0.5V | 6 | |
| Output clamping current | IOK | -20 | 20 | mA | VO < -0.5V or VO > VCC+0.5V | 6 | |
| Output current | IO | -35 | 35 | mA | VO= -0.5V to (VCC+0.5V) | 6 | |
| Storage temperature | Tstg | 150 | ℃ | 6 | |||
| Total power dissipation | Ptot | 500 | mW | 6 | |||
| Soldering temperature | TL | 260 | ℃ | 10 s | 6 | ||
| Supply voltage | VCC | 2 | 5 | 6 | V | 6 | |
| Input voltage | VI | 0 | V | maximum is VCC (not a number) | 6 | ||
| Output voltage | VO | 0 | V | maximum is VCC (not a number) | 6 | ||
| Input transition rise and fall rate | Δt/ΔV | 625 | ns/V | VCC=2.0V | 6 | ||
| Input transition rise and fall rate | Δt/ΔV | 139 | ns/V | VCC=4.5V | 6 | ||
| Input transition rise and fall rate | Δt/ΔV | 83 | ns/V | VCC=6.0V | 6 | ||
| Ambient temperature | Tamb | -20 | 85 | ℃ | 6 | ||
| HIGH-level input voltage | VIH | 3.15 | V | Tamb=-20℃ to +85℃; VCC=4.5V | 8 | ||
| HIGH-level input voltage | VIH | 4.2 | V | Tamb=-20℃ to +85℃; VCC=6.0V | 8 | ||
| LOW-level input voltage | VIL | 1.35 | V | Tamb=-20℃ to +85℃; VCC=4.5V | 8 | ||
| LOW-level input voltage | VIL | 1.8 | V | Tamb=-20℃ to +85℃; VCC=6.0V | 8 | ||
| HIGH-level output voltage | VOH | 1.9 | V | Tamb=-20℃ to +85℃; VI=VIH or VIL; IO=-20uA; VCC=2.0V | 8 | ||
| HIGH-level output voltage | VOH | 4.4 | V | Tamb=-20℃ to +85℃; VI=VIH or VIL; IO=-20uA; VCC=4.5V | 8 | ||
| HIGH-level output voltage | VOH | 3.84 | V | Tamb=-20℃ to +85℃; VI=VIH or VIL; IO=-6.0mA; VCC=4.5V | 8 | ||
| HIGH-level output voltage | VOH | 5.34 | V | Tamb=-20℃ to +85℃; VI=VIH or VIL; IO=-7.8mA; VCC=6.0V | 8 | ||
| LOW-level output voltage | VOL | 0.1 | V | Tamb=-20℃ to +85℃; VI=VIH or VIL; IO=20uA; VCC=2.0V | 8 | ||
| LOW-level output voltage | VOL | 0.33 | V | Tamb=-20℃ to +85℃; VI=VIH or VIL; IO=6.0mA; VCC=4.5V | 8 | ||
| Input leakage current | II | -1 | 1 | uA | VI=VCC or GND; VCC=6.0V | 8 | |
| OFF-state output current | IOZ | -5 | 5 | uA | VI=VIH or VIL; VCC=6.0V; VO=VCC or GND | 8 | |
| Supply current | ICC | 80 | uA | VI=VCC or GND; IO=0A; VCC=6.0V | 8 | ||
| Propagation delay Dn to Qn | tpd | 190 | ns | see Figure 6; VCC=2.0V | 10 | ||
| Propagation delay Dn to Qn | tpd | 38 | ns | see Figure 6; VCC=4.5V | 10 | ||
| Propagation delay Dn to Qn | tpd | 33 | ns | see Figure 6; VCC=6.0V | 10 | ||
| Propagation delay LE to Qn | tpd | 175 | ns | see Figure 7; VCC=2.0V | 10 | ||
| Propagation delay LE to Qn | tpd | 35 | ns | see Figure 7; VCC=4.5V | 10 | ||
| Propagation delay LE to Qn | tpd | 30 | ns | see Figure 7; VCC=6.0V | 10 | ||
| OE to Qn enable time | ten | 190 | ns | see Figure 8; VCC=2.0V | 10 | ||
| OE to Qn enable time | ten | 38 | ns | see Figure 8; VCC=4.5V | 10 | ||
| OE to Qn enable time | ten | 33 | ns | see Figure 8; VCC=6.0V | 10 | ||
| Transition time Qn | t | 75 | ns | see Figure 6; VCC=2.0V | 10 | ||
| Transition time Qn | t | 15 | ns | see Figure 6; VCC=4.5V | 10 | ||
| Transition time Qn | t | 13 | ns | see Figure 6; VCC=6.0V | 10 | ||
| Pulse width LE HIGH | tW | 100 | ns | see Figure 7; VCC=2.0V | 10 | ||
| Pulse width LE HIGH | tW | 20 | ns | see Figure 7; VCC=4.5V | 10 | ||
| Pulse width LE HIGH | tW | 17 | ns | see Figure 7; VCC=6.0V | 10 | ||
| Set-up time Dn to LE | tsu | 65 | ns | see Figure 9; VCC=2.0V | 10 | ||
| Set-up time Dn to LE | tsu | 13 | ns | see Figure 9; VCC=4.5V | 10 | ||
| Set-up time Dn to LE | tsu | 11 | ns | see Figure 9; VCC=6.0V | 10 | ||
| Hold time Dn to LE | th | 5 | ns | see Figure 9; VCC=2.0V | 10 |
CAD (KiCad official)
- Symbol:
SN74LS573N - Footprint:
Package_DIP:DIP-20_W7.62mm - 3D model: DIP-20 (KiCad packages3D, STEP)
- 3D model files:
sn74ls573n-etched.step/sn74ls573n-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);sn74ls573n.step/sn74ls573n.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: XBLW datasheet (17 pp, sha256
7093208ab66548b3, retrieved 2026-10-14, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).