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SN74LS541DWR

Texas Instruments · Buffers, Drivers, Receivers, Transceivers · SOIC-20-300mil

SN74LS541DWR from Texas Instruments, in a SOIC-20-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 G1 input Active-low output-enable input of the 2-input NOR control gate; if either G1 or G2 is high, all eight outputs are in the high-impedance state.
2 A1 input Data input 1 with hysteresis, non-inverting in the 'LS541, driving output Y1 (pin 18).
3 A2 input Data input 2 with hysteresis, non-inverting in the 'LS541, driving output Y2 (pin 17).
4 A3 input Data input 3 with hysteresis, non-inverting in the 'LS541, driving output Y3 (pin 16).
5 A4 input Data input 4 with hysteresis, non-inverting in the 'LS541, driving output Y4 (pin 15).
6 A5 input Data input 5 with hysteresis, non-inverting in the 'LS541, driving output Y5 (pin 14).
7 A6 input Data input 6 with hysteresis, non-inverting in the 'LS541, driving output Y6 (pin 13).
8 A7 input Data input 7 with hysteresis, non-inverting in the 'LS541, driving output Y7 (pin 12).
9 A8 input Data input 8 with hysteresis, non-inverting in the 'LS541, driving output Y8 (pin 11).
10 GND power_in Ground; the datasheet gives all voltage values with respect to the network ground terminal.
11 Y8 tri_state 3-state output 8 following A8 (true data), rated 24 mA sink and -15 mA source for the SN74LS541, high-impedance when G1 or G2 is high.
12 Y7 tri_state 3-state output 7 following A7 (true data), rated 24 mA sink and -15 mA source for the SN74LS541, high-impedance when G1 or G2 is high.
13 Y6 tri_state 3-state output 6 following A6 (true data), rated 24 mA sink and -15 mA source for the SN74LS541, high-impedance when G1 or G2 is high.
14 Y5 tri_state 3-state output 5 following A5 (true data), rated 24 mA sink and -15 mA source for the SN74LS541, high-impedance when G1 or G2 is high.
15 Y4 tri_state 3-state output 4 following A4 (true data), rated 24 mA sink and -15 mA source for the SN74LS541, high-impedance when G1 or G2 is high.
16 Y3 tri_state 3-state output 3 following A3 (true data), rated 24 mA sink and -15 mA source for the SN74LS541, high-impedance when G1 or G2 is high.
17 Y2 tri_state 3-state output 2 following A2 (true data), rated 24 mA sink and -15 mA source for the SN74LS541, high-impedance when G1 or G2 is high.
18 Y1 tri_state 3-state output 1 following A1 (true data), rated 24 mA sink and -15 mA source for the SN74LS541, high-impedance when G1 or G2 is high.
19 G2 input Active-low output-enable input of the 2-input NOR control gate; if either G1 or G2 is high, all eight outputs are in the high-impedance state.
20 VCC power_in Supply voltage, recommended 4.75 V to 5.25 V (5 V nominal) for the SN74LS541, absolute maximum 7 V.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-20-300mil
Category Logic
Pins 20

CAD (KiCad official)

  • Symbol: SN74LS541DWR
  • Footprint: Package_SO:SOIC-20W_7.5x12.8mm_P1.27mm
  • 3D model: SOIC-20-300mil (KiCad packages3D, STEP)
  • 3D model files: sn74ls541dwr-etched.step / sn74ls541dwr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74ls541dwr.step / sn74ls541dwr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (24 pp, sha256 9788278e6b6fa31f, retrieved 2026-11-06, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF