component
SN74LS540DWR
Public Made by Adomby adom
Texas Instruments Buffers, Drivers, Receivers, Transceivers, SOIC-20-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
Open in new tab ↗
Loads on click. Unloads only if this page sits in the background.
Symbol & Footprint
Schematic Symbol
Open full view ↗Loads on click. Unloads only if this page sits in the background.
PCB Footprint
Open full view ↗Loads on click. Unloads only if this page sits in the background.
Datasheet
Open in new tab ↗Loads on click. Unloads only if this page sits in the background.
README
markdownSN74LS540DWR
Texas Instruments · Buffers, Drivers, Receivers, Transceivers · SOIC-20-300mil
SN74LS540DWR from Texas Instruments, in a SOIC-20-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | G1 | input | Active-low output enable 1; if either G1 or G2 is high, all eight outputs are in the high-impedance state. |
| 2 | A1 | input | Data input 1 with hysteresis, inverted to Y1 on the 'LS540. |
| 3 | A2 | input | Data input 2 with hysteresis, inverted to Y2 on the 'LS540. |
| 4 | A3 | input | Data input 3 with hysteresis, inverted to Y3 on the 'LS540. |
| 5 | A4 | input | Data input 4 with hysteresis, inverted to Y4 on the 'LS540. |
| 6 | A5 | input | Data input 5 with hysteresis, inverted to Y5 on the 'LS540. |
| 7 | A6 | input | Data input 6 with hysteresis, inverted to Y6 on the 'LS540. |
| 8 | A7 | input | Data input 7 with hysteresis, inverted to Y7 on the 'LS540. |
| 9 | A8 | input | Data input 8 with hysteresis, inverted to Y8 on the 'LS540. |
| 10 | GND | power_in | Ground; voltage values are specified with respect to this network ground terminal. |
| 11 | Y8 | tri_state | 3-state inverting output 8, rated 24 mA sink and -15 mA source for SN74LS540. |
| 12 | Y7 | tri_state | 3-state inverting output 7, rated 24 mA sink and -15 mA source for SN74LS540. |
| 13 | Y6 | tri_state | 3-state inverting output 6, rated 24 mA sink and -15 mA source for SN74LS540. |
| 14 | Y5 | tri_state | 3-state inverting output 5, rated 24 mA sink and -15 mA source for SN74LS540. |
| 15 | Y4 | tri_state | 3-state inverting output 4, rated 24 mA sink and -15 mA source for SN74LS540. |
| 16 | Y3 | tri_state | 3-state inverting output 3, rated 24 mA sink and -15 mA source for SN74LS540. |
| 17 | Y2 | tri_state | 3-state inverting output 2, rated 24 mA sink and -15 mA source for SN74LS540. |
| 18 | Y1 | tri_state | 3-state inverting output 1, rated 24 mA sink and -15 mA source for SN74LS540. |
| 19 | G2 | input | Active-low output enable 2; if either G1 or G2 is high, all eight outputs are in the high-impedance state. |
| 20 | VCC | power_in | Supply voltage; absolute maximum 7 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-20-300mil |
| Category | Logic |
| Pins | 20 |
CAD (KiCad official)
- Symbol:
SN74LS540DWR - Footprint:
Package_SO:SOIC-20W_7.5x12.8mm_P1.27mm - 3D model: SOIC-20-300mil (KiCad packages3D, STEP)
- 3D model files:
sn74ls540dwr-etched.step/sn74ls540dwr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);sn74ls540dwr.step/sn74ls540dwr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (24 pp, sha256
9788278e6b6fa31f, retrieved 2026-10-08, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(vision), consensusclaude-opus-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).