component
SN74LS374DWR
Public Made by Adomby adom
lingxingic Flip Flops, SOP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
| Name | Last updated |
|---|---|
| docs | 5d ago |
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| page.json | 5d ago |
| README.md | 5d ago |
| sn74ls374dwr-etched.glb | 5d ago |
| sn74ls374dwr-etched.step | 5d ago |
| sn74ls374dwr-hero.glb | 5d ago |
| sn74ls374dwr-hero.overlay.json | 5d ago |
| sn74ls374dwr.glb | 5d ago |
| sn74ls374dwr.kicad_mod | 5d ago |
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| sn74ls374dwr.step | 5d ago |
SN74LS374DWR
lingxingic · Flip Flops · SOP-20
SN74LS374DWR from lingxingic, in a SOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | OE | input | Active-low output enable input; a high level puts the outputs in high impedance without affecting flip-flop state. |
| 2 | Q0 | tri_state | Data output 0 (non-inverting 3-state output). |
| 3 | D0 | input | Data input 0. |
| 4 | D1 | input | Data input 1. |
| 5 | Q1 | tri_state | Data output 1 (non-inverting 3-state output). |
| 6 | Q2 | tri_state | Data output 2 (non-inverting 3-state output). |
| 7 | D2 | input | Data input 2. |
| 8 | D3 | input | Data input 3. |
| 9 | Q3 | tri_state | Data output 3 (non-inverting 3-state output). |
| 10 | GND | power_in | Ground (0V). |
| 11 | CP | input | Clock input, low-to-high edge triggered. |
| 12 | Q4 | tri_state | Data output 4 (non-inverting 3-state output). |
| 13 | D4 | input | Data input 4. |
| 14 | D5 | input | Data input 5. |
| 15 | Q5 | tri_state | Data output 5 (non-inverting 3-state output). |
| 16 | Q6 | tri_state | Data output 6 (non-inverting 3-state output). |
| 17 | D6 | input | Data input 6. |
| 18 | D7 | input | Data input 7. |
| 19 | Q7 | tri_state | Data output 7 (non-inverting 3-state output). |
| 20 | VCC | power_in | Supply voltage; recommended 2.0V to 6.0V (5.0V typical), absolute maximum -0.5V to +7.0V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | lingxingic |
| Package | SOP-20 |
| Category | Logic |
| Pins | 20 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage | VCC | -0.5 | 7 | V | Tamb=25℃, GND=0V | 8 | |
| Input clamp current | IIK | -20 | 20 | mA | VI<-0.5V or VI>VCC+0.5V | 8 | |
| Output clamp current | IOK | -20 | 20 | mA | VO<-0.5V or VO>VCC+0.5V | 8 | |
| Output current | IO | -35 | 35 | mA | -0.5V<VO<VCC+0.5V | 8 | |
| Supply current | ICC | 70 | mA | 8 | |||
| Ground current | IGND | -70 | mA | 8 | |||
| Storage temperature | Tstg | -65 | 150 | ℃ | 8 | ||
| Total power dissipation | Ptot | 500 | mW | 8 | |||
| Soldering temperature | TL | 260 | ℃ | 10 s, SOP/TSSOP | 8 | ||
| Supply voltage | VCC | 2 | 5 | 6 | V | 9 | |
| Input voltage | VI | 0 | V | max is VCC | 9 | ||
| Output voltage | VO | 0 | V | max is VCC | 9 | ||
| Input rise and fall slew rate | Δt/ΔV | 625 | ns/V | VCC=2.0V | 9 | ||
| Input rise and fall slew rate | Δt/ΔV | 1.67 | 139 | ns/V | VCC=4.5V | 9 | |
| Input rise and fall slew rate | Δt/ΔV | 83 | ns/V | VCC=6.0V | 9 | ||
| Operating ambient temperature | Tamb | -40 | 125 | ℃ | 9 | ||
| High-level input voltage | VIH | 1.5 | V | VCC=2.0V; Tamb=-40℃~+125℃ | 11 | ||
| High-level input voltage | VIH | 3.15 | V | VCC=4.5V; Tamb=-40℃~+125℃ | 11 | ||
| High-level input voltage | VIH | 4.2 | V | VCC=6.0V; Tamb=-40℃~+125℃ | 11 | ||
| Low-level input voltage | VIL | 0.5 | V | VCC=2.0V; Tamb=-40℃~+125℃ | 11 | ||
| Low-level input voltage | VIL | 1.35 | V | VCC=4.5V; Tamb=-40℃~+125℃ | 11 | ||
| Low-level input voltage | VIL | 1.8 | V | VCC=6.0V; Tamb=-40℃~+125℃ | 11 | ||
| High-level output voltage | VOH | 1.9 | V | VI=VIH or VIL; IO=-20uA; VCC=2.0V | 11 | ||
| High-level output voltage | VOH | 4.4 | V | VI=VIH or VIL; IO=-20uA; VCC=4.5V | 11 | ||
| High-level output voltage | VOH | 5.9 | V | VI=VIH or VIL; IO=-20uA; VCC=6.0V | 11 | ||
| High-level output voltage | VOH | 3.7 | V | VI=VIH or VIL; IO=-6.0mA; VCC=4.5V | 11 | ||
| High-level output voltage | VOH | 5.2 | V | VI=VIH or VIL; IO=-7.8mA; VCC=6.0V | 11 | ||
| Low-level output voltage | VOL | 0.1 | V | VI=VIH or VIL; IO=20uA; VCC=2.0V | 11 | ||
| Low-level output voltage | VOL | 0.4 | V | VI=VIH or VIL; IO=6.0mA; VCC=4.5V | 11 | ||
| Input leakage current | II | -1 | 1 | uA | VI=VCC or GND; VCC=6.0V | 11 | |
| Off-state output current | IOZ | -10 | 10 | uA | VI=VIH or VIL; VCC=6.0V; VO=VCC or GND | 11 | |
| Quiescent supply current | ICC | 160 | uA | VI=VCC or GND; IO=0A; VCC=6.0V | 11 | ||
| CP to Qn propagation delay | tpd | 250 | ns | VCC=2.0V; Tamb=-40℃~+125℃ | 15 | ||
| CP to Qn propagation delay | tpd | 50 | ns | VCC=4.5V; Tamb=-40℃~+125℃ | 15 | ||
| CP to Qn propagation delay | tpd | 43 | ns | VCC=6.0V; Tamb=-40℃~+125℃ | 15 | ||
| OE to Qn enable time | ten | 225 | ns | VCC=2.0V; Tamb=-40℃~+125℃ | 15 | ||
| OE to Qn enable time | ten | 45 | ns | VCC=4.5V; Tamb=-40℃~+125℃ | 15 | ||
| OE to Qn enable time | ten | 38 | ns | VCC=6.0V; Tamb=-40℃~+125℃ | 15 | ||
| OE to Qn disable time | tdis | 225 | ns | VCC=2.0V; Tamb=-40℃~+125℃ | 15 | ||
| OE to Qn disable time | tdis | 45 | ns | VCC=4.5V; Tamb=-40℃~+125℃ | 15 | ||
| OE to Qn disable time | tdis | 38 | ns | VCC=6.0V; Tamb=-40℃~+125℃ | 15 | ||
| Transition time | tt | 90 | ns | Qn output; VCC=2.0V; Tamb=-40℃~+125℃ | 15 | ||
| Transition time | tt | 18 | ns | Qn output; VCC=4.5V; Tamb=-40℃~+125℃ | 15 | ||
| Transition time | tt | 15 | ns | Qn output; VCC=6.0V; Tamb=-40℃~+125℃ | 15 | ||
| Pulse width | tW | 120 | ns | CP high or low; VCC=2.0V; Tamb=-40℃~+125℃ | 15 | ||
| Pulse width | tW | 24 | ns | CP high or low; VCC=4.5V; Tamb=-40℃~+125℃ | 15 | ||
| Pulse width | tW | 20 | ns | CP high or low; VCC=6.0V; Tamb=-40℃~+125℃ | 15 | ||
| Dn to CP setup time | tsu | 90 | ns | VCC=2.0V; Tamb=-40℃~+125℃ | 15 | ||
| Dn to CP setup time | tsu | 18 | ns | VCC=4.5V; Tamb=-40℃~+125℃ | 15 | ||
| Dn to CP setup time | tsu | 15 | ns | VCC=6.0V; Tamb=-40℃~+125℃ | 15 | ||
| Dn to CP hold time | th | 5 | ns | VCC=2.0V; Tamb=-40℃~+125℃ | 15 | ||
| Maximum frequency | fmax | 4 | MHz | CP input; VCC=2.0V; Tamb=-40℃~+125℃ | 15 | ||
| Maximum frequency | fmax | 20 | MHz | CP input; VCC=4.5V; Tamb=-40℃~+125℃ | 15 | ||
| Maximum frequency | fmax | 24 | MHz | CP input; VCC=6.0V; Tamb=-40℃~+125℃ | 15 |
CAD (KiCad official)
- Symbol:
SN74LS374DWR - Footprint:
Package_SO:SOP-20_7.5x12.8mm_P1.27mm - 3D model: SOP-20, generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 2.65 mm nominal SOIC height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
- 3D model files:
sn74ls374dwr-etched.step/sn74ls374dwr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);sn74ls374dwr.step/sn74ls374dwr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: lingxingic datasheet (22 pp, sha256
0330377b79f2eb40, retrieved 2026-10-23, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).