Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity

3D Model

Open in new tab ↗

Loads when you scroll to it. Unloads after 5 minutes in the background.

Symbol & Footprint

Schematic Symbol

Open full view ↗

Loads when you scroll to it. Unloads after 5 minutes in the background.

PCB Footprint

Open full view ↗

Loads when you scroll to it. Unloads after 5 minutes in the background.

Datasheet

Open in new tab ↗

Loads when you scroll to it. Unloads after 5 minutes in the background.

Download PDF

Contents

Pinout
Key specifications
CAD (KiCad official)
Provenance

README

markdown

SN74LS373N

Texas Instruments · Latches · DIP-20

SN74LS373N from Texas Instruments, in a DIP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	OC	input	Buffered output-control input: when low the eight outputs show normal logic levels, and when high they go to the high-impedance state without affecting the latch contents.
2	1Q	tri_state	Latch 1 3-state bus-driving output, which follows 1D while C is high and holds the latched level when C goes low.
3	1D	input	Latch 1 data input, sampled while C is high on the ’LS373.
4	2D	input	Latch 2 data input, sampled while C is high on the ’LS373.
5	2Q	tri_state	Latch 2 3-state bus-driving output, designed for driving highly capacitive or low-impedance loads.
6	3Q	tri_state	Latch 3 3-state bus-driving output, designed for driving highly capacitive or low-impedance loads.
7	3D	input	Latch 3 data input, sampled while C is high on the ’LS373.
8	4D	input	Latch 4 data input, sampled while C is high on the ’LS373.
9	4Q	tri_state	Latch 4 3-state bus-driving output, designed for driving highly capacitive or low-impedance loads.
10	GND	power_in	Ground reference pin; the pages provided do not state a voltage or current rating for this pin.
11	C	input	Latch enable input for the ’LS373: while high the Q outputs follow D, and when taken low the output is latched at the set-up data level (Schmitt-trigger hysteresis applies only to ’S373/’S374).
12	5Q	tri_state	Latch 5 3-state bus-driving output, designed for driving highly capacitive or low-impedance loads.
13	5D	input	Latch 5 data input, sampled while C is high on the ’LS373.
14	6D	input	Latch 6 data input, sampled while C is high on the ’LS373.
15	6Q	tri_state	Latch 6 3-state bus-driving output, designed for driving highly capacitive or low-impedance loads.
16	7Q	tri_state	Latch 7 3-state bus-driving output, designed for driving highly capacitive or low-impedance loads.
17	7D	input	Latch 7 data input, sampled while C is high on the ’LS373.
18	8D	input	Latch 8 data input, sampled while C is high on the ’LS373.
19	8Q	tri_state	Latch 8 3-state bus-driving output, designed for driving highly capacitive or low-impedance loads.
20	VCC	power_in	Supply pin; the pages provided do not state a supply voltage range for this pin.

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	DIP-20
Category	Logic
Pins	20

CAD (KiCad official)

Symbol: SN74LS373N
Footprint: Package_DIP:DIP-20_W7.62mm
3D model: DIP-20 (KiCad packages3D, STEP)
3D model files: sn74ls373n-etched.step / sn74ls373n-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74ls373n.step / sn74ls373n.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (34 pp, sha256 5d2c396010d2b304, retrieved 2026-10-11, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF