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SN74LS373DW

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Texas Instruments Latches, SOIC-20-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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SN74LS373DW

Texas Instruments · Latches · SOIC-20-300mil

SN74LS373DW from Texas Instruments, in a SOIC-20-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 OC input Buffered output-control input that places the eight outputs in either a normal logic state or the high-impedance state without affecting internal latch operation.
2 1Q tri_state Channel 1 3-state output that follows the 1D input while C is high and holds the latched level when C is low.
3 1D input Channel 1 data input to the D-type latch.
4 2D input Channel 2 data input to the D-type latch.
5 2Q tri_state Channel 2 3-state output that follows the 2D input while C is high and holds the latched level when C is low.
6 3Q tri_state Channel 3 3-state output that follows the 3D input while C is high and holds the latched level when C is low.
7 3D input Channel 3 data input to the D-type latch.
8 4D input Channel 4 data input to the D-type latch.
9 4Q tri_state Channel 4 3-state output that follows the 4D input while C is high and holds the latched level when C is low.
10 GND power_in Ground pin.
11 C input Latch enable input; while high the Q outputs follow the D inputs, and when taken low the outputs latch the data that was set up.
12 5Q tri_state Channel 5 3-state output that follows the 5D input while C is high and holds the latched level when C is low.
13 5D input Channel 5 data input to the D-type latch.
14 6D input Channel 6 data input to the D-type latch.
15 6Q tri_state Channel 6 3-state output that follows the 6D input while C is high and holds the latched level when C is low.
16 7Q tri_state Channel 7 3-state output that follows the 7D input while C is high and holds the latched level when C is low.
17 7D input Channel 7 data input to the D-type latch.
18 8D input Channel 8 data input to the D-type latch.
19 8Q tri_state Channel 8 3-state output that follows the 8D input while C is high and holds the latched level when C is low.
20 VCC power_in Positive supply voltage pin.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-20-300mil
Category Logic ICs
Pins 20

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VCC 4.75 5 5.25 V SN74LS' 6
High-level output voltage VOH 5.5 V SN74LS' 6
High-level output current IOH -2.6 mA SN74LS' 6
Low-level output current IOL 24 mA SN74LS' 6
Pulse duration, enable high tw 15 ns CLK high 6
Pulse duration, enable low tw 15 ns CLK low 6
Data setup time tsu 5 ns 'LS373, falling edge of C 6
Data hold time th 20 ns 'LS373, falling edge of C 6
Operating free-air temperature TA 0 70 °C SN74LS' 6
Supply voltage VCC 7 V 'LS devices 6
Input voltage VI 7 V 'LS devices 6
Off-state output voltage 5.5 V 'LS devices 6
Storage temperature range Tstg -65 150 °C 6
Package thermal impedance, DW package θJA 58 °C/W DW package, JESD 51-7 6
High-level input voltage VIH 2 V 7
Low-level input voltage VIL 0.8 V 7
Input clamp voltage VIK -1.5 V VCC = MIN, II = -18 mA 7
High-level output voltage VOH 2.4 3.1 V VCC = MIN, VIH = 2 V, VIL = VIL max, IOH = MAX 7
Low-level output voltage VOL 0.25 0.4 V VCC = MIN, VIH = 2 V, VIL = VIL max, IOL = 12 mA 7
Low-level output voltage VOL 0.35 0.5 V VCC = MIN, VIH = 2 V, VIL = VIL max, IOL = 24 mA 7
Off-state output current, high-level voltage applied IOZH 20 µA VCC = MAX, VIH = 2 V, VO = 2.7 V 7
Off-state output current, low-level voltage applied IOZL -20 µA VCC = MAX, VIH = 2 V, VO = 0.4 V 7
Input current at maximum input voltage II 0.1 mA VCC = MAX, VI = 7 V 7
High-level input current IIH 20 µA VCC = MAX, VI = 2.7 V 7
Low-level input current IIL -0.4 mA VCC = MAX, VI = 0.4 V 7
Short-circuit output current IOS -30 -130 mA VCC = MAX 7
Supply current ICC 24 40 mA VCC = MAX, Output control at 4.5 V, 'LS373 7
Maximum clock frequency fmax 35 50 MHz RL = 667 Ω, CL = 45 pF, VCC = 5 V, TA = 25°C 7
Propagation delay, data to Q, low-to-high tPLH 12 18 ns RL = 667 Ω, CL = 45 pF, 'LS373 7
Propagation delay, data to Q, high-to-low tPHL 12 18 ns RL = 667 Ω, CL = 45 pF, 'LS373 7
Propagation delay, C to Q, low-to-high tPLH 20 30 ns RL = 667 Ω, CL = 45 pF, 'LS373 7
Propagation delay, C to Q, high-to-low tPHL 18 30 ns RL = 667 Ω, CL = 45 pF, 'LS373 7
Output enable time to high level tPZH 15 28 ns RL = 667 Ω, CL = 45 pF, 'LS373 7
Output enable time to low level tPZL 25 36 ns RL = 667 Ω, CL = 45 pF, 'LS373 7
Output disable time from high level tPHZ 15 25 ns RL = 667 Ω, CL = 5 pF, 'LS373 7
Output disable time from low level tPLZ 12 20 ns RL = 667 Ω, CL = 5 pF, 'LS373 7

CAD (KiCad official)

  • Symbol: SN74LS373DW
  • Footprint: Package_SO:SOIC-20W_7.5x12.8mm_P1.27mm
  • 3D model: SOIC-20-300mil (KiCad packages3D, STEP)
  • 3D model files: sn74ls373dw-etched.step / sn74ls373dw-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74ls373dw.step / sn74ls373dw.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (31 pp, sha256 29beb6509e46e6e4, retrieved 2026-10-23, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF