component
SN74LS273N
Public Made by Adomby adom
lingxingic Flip Flops, DIP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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SN74LS273N
lingxingic · Flip Flops · DIP-20
SN74LS273N from lingxingic, in a DIP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | MR | input | Active-low master reset input; when driven low, all Qn outputs go low regardless of the clock and data inputs. |
| 2 | Q0 | output | Flip-flop 0 output, which takes the state of D0 on the rising edge of CP and goes low when MR is low. |
| 3 | D0 | input | Data input to flip-flop 0, sampled on the rising edge of CP and meeting the setup and hold times stated in the datasheet. |
| 4 | D1 | input | Data input to flip-flop 1, sampled on the rising edge of CP and meeting the setup and hold times stated in the datasheet. |
| 5 | Q1 | output | Flip-flop 1 output, which takes the state of D1 on the rising edge of CP and goes low when MR is low. |
| 6 | Q2 | output | Flip-flop 2 output, which takes the state of D2 on the rising edge of CP and goes low when MR is low. |
| 7 | D2 | input | Data input to flip-flop 2, sampled on the rising edge of CP and meeting the setup and hold times stated in the datasheet. |
| 8 | D3 | input | Data input to flip-flop 3, sampled on the rising edge of CP and meeting the setup and hold times stated in the datasheet. |
| 9 | Q3 | output | Flip-flop 3 output, which takes the state of D3 on the rising edge of CP and goes low when MR is low. |
| 10 | GND | power_in | Ground reference, 0 V. |
| 11 | CP | input | Clock input; all eight flip-flops are triggered on its rising edge. |
| 12 | Q4 | output | Flip-flop 4 output, which takes the state of D4 on the rising edge of CP and goes low when MR is low. |
| 13 | D4 | input | Data input to flip-flop 4, sampled on the rising edge of CP and meeting the setup and hold times stated in the datasheet. |
| 14 | D5 | input | Data input to flip-flop 5, sampled on the rising edge of CP and meeting the setup and hold times stated in the datasheet. |
| 15 | Q5 | output | Flip-flop 5 output, which takes the state of D5 on the rising edge of CP and goes low when MR is low. |
| 16 | Q6 | output | Flip-flop 6 output, which takes the state of D6 on the rising edge of CP and goes low when MR is low. |
| 17 | D6 | input | Data input to flip-flop 6, sampled on the rising edge of CP and meeting the setup and hold times stated in the datasheet. |
| 18 | D7 | input | Data input to flip-flop 7, sampled on the rising edge of CP and meeting the setup and hold times stated in the datasheet. |
| 19 | Q7 | output | Flip-flop 7 output, which takes the state of D7 on the rising edge of CP and goes low when MR is low. |
| 20 | VCC | power_in | Supply voltage; recommended range 2.0 V to 6.0 V (typical 5.0 V), absolute maximum 7.0 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | lingxingic |
| Package | DIP-20 |
| Category | Logic |
| Pins | 20 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage | VCC | -0.5 | 7 | V | 8 | ||
| Input clamp current | IIK | -20 | 20 | mA | VI<-0.5V 或 VI>VCC+0.5V | 8 | |
| Output clamp current | IOK | -20 | 20 | mA | VO<-0.5V 或 VO>VCC+0.5V | 8 | |
| Output current | IO | -25 | 25 | mA | -0.5V<VO<VCC+0.5V | 8 | |
| Supply current | ICC | 50 | mA | 8 | |||
| Ground current | IGND | -50 | mA | 8 | |||
| Storage temperature | Tstg | -65 | 150 | ℃ | 8 | ||
| Total power dissipation | Ptot | 500 | mW | 8 | |||
| Soldering temperature (DIP) | TL | 245 | ℃ | 10 s | 8 | ||
| Supply voltage | VCC | 2 | 5 | 6 | V | 9 | |
| Input voltage | VI | 0 | V | 9 | |||
| Output voltage | VO | 0 | V | 9 | |||
| Input rise and fall rate | Δt/ΔV | 625 | ns/V | VCC=2.0V | 9 | ||
| Input rise and fall rate | Δt/ΔV | 1.67 | 139 | ns/V | VCC=4.5V | 9 | |
| Input rise and fall rate | Δt/ΔV | 83 | ns/V | VCC=6.0V | 9 | ||
| Operating ambient temperature | Tamb | -40 | 125 | ℃ | 9 | ||
| High-level input voltage | VIH | 1.5 | 1.2 | V | Tamb=25℃; VCC=2.0V | 9 | |
| High-level input voltage | VIH | 3.15 | 2.4 | V | Tamb=25℃; VCC=4.5V | 9 | |
| High-level input voltage | VIH | 4.2 | 3.2 | V | Tamb=25℃; VCC=6.0V | 9 | |
| Low-level input voltage | VIL | 0.8 | 0.5 | V | Tamb=25℃; VCC=2.0V | 9 | |
| Low-level input voltage | VIL | 2.1 | 1.35 | V | Tamb=25℃; VCC=4.5V | 9 | |
| Low-level input voltage | VIL | 2.8 | 1.8 | V | Tamb=25℃; VCC=6.0V | 9 | |
| High-level output voltage | VOH | 1.9 | 2 | V | Tamb=25℃; VI=VIH或VIL; IO=-20uA；VCC=2.0V | 9 | |
| High-level output voltage | VOH | 4.4 | 4.5 | V | Tamb=25℃; VI=VIH或VIL; IO=-20uA；VCC=4.5V | 9 | |
| High-level output voltage | VOH | 5.9 | 6 | V | Tamb=25℃; VI=VIH或VIL; IO=-20uA；VCC=6.0V | 9 | |
| High-level output voltage | VOH | 3.98 | 4.32 | V | Tamb=25℃; VI=VIH或VIL; IO=-4.0mA；VCC=4.5V | 9 | |
| High-level output voltage | VOH | 5.48 | 5.81 | V | Tamb=25℃; VI=VIH或VIL; IO=-5.2mA；VCC=6.0V | 9 | |
| Low-level output voltage | VOL | 0 | 0.1 | V | Tamb=25℃; VI=VIH或VIL; IO=20uA；VCC=2.0V | 9 | |
| Low-level output voltage | VOL | 0.15 | 0.26 | V | Tamb=25℃; VI=VIH或VIL; IO=4.0mA；VCC=4.5V | 9 | |
| Low-level output voltage | VOL | 0.16 | 0.26 | V | Tamb=25℃; VI=VIH或VIL; IO=5.2mA；VCC=6.0V | 9 | |
| Input leakage current | II | -1 | 1 | uA | Tamb=25℃; VI=VCC或GND; VCC=6.0V | 9 | |
| Quiescent supply current | ICC | 8 | uA | Tamb=25℃; VI=VCC或GND; IO=0A; VCC=6.0V | 9 | ||
| High-level input voltage | VIH | 1.5 | V | Tamb=-40℃～+125℃; VCC=2.0V | 11 | ||
| High-level input voltage | VIH | 3.15 | V | Tamb=-40℃～+125℃; VCC=4.5V | 11 | ||
| High-level input voltage | VIH | 4.2 | V | Tamb=-40℃～+125℃; VCC=6.0V | 11 | ||
| Low-level input voltage | VIL | 0.5 | V | Tamb=-40℃～+125℃; VCC=2.0V | 11 | ||
| Low-level input voltage | VIL | 1.35 | V | Tamb=-40℃～+125℃; VCC=4.5V | 11 | ||
| Low-level input voltage | VIL | 1.8 | V | Tamb=-40℃～+125℃; VCC=6.0V | 11 | ||
| High-level output voltage | VOH | 1.9 | V | Tamb=-40℃～+125℃; VI=VIH或VIL; IO=-20uA；VCC=2.0V | 11 | ||
| High-level output voltage | VOH | 4.4 | V | Tamb=-40℃～+125℃; VI=VIH或VIL; IO=-20uA；VCC=4.5V | 11 | ||
| High-level output voltage | VOH | 5.9 | V | Tamb=-40℃～+125℃; VI=VIH或VIL; IO=-20uA；VCC=6.0V | 11 | ||
| High-level output voltage | VOH | 3.7 | V | Tamb=-40℃～+125℃; VI=VIH或VIL; IO=-4.0mA；VCC=4.5V | 11 | ||
| High-level output voltage | VOH | 5.2 | V | Tamb=-40℃～+125℃; VI=VIH或VIL; IO=-5.2mA；VCC=6.0V | 11 | ||
| Low-level output voltage | VOL | 0.1 | V | Tamb=-40℃～+125℃; VI=VIH或VIL; IO=20uA；VCC=2.0V | 11 | ||
| Low-level output voltage | VOL | 0.4 | V | Tamb=-40℃～+125℃; VI=VIH或VIL; IO=4.0mA；VCC=4.5V | 11 | ||
| Input leakage current | II | -1 | 1 | uA | Tamb=-40℃～+125℃; VI=VCC或GND; VCC=6.0V | 11 | |
| Quiescent supply current | ICC | 160 | uA | Tamb=-40℃～+125℃; VI=VCC或GND; IO=0A; VCC=6.0V | 11 |
CAD (KiCad official)
- Symbol:
SN74LS273N - Footprint:
Package_DIP:DIP-20_W7.62mm - 3D model: DIP-20 (KiCad packages3D, STEP)
- 3D model files:
sn74ls273n-etched.step/sn74ls273n-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);sn74ls273n.step/sn74ls273n.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: lingxingic datasheet (21 pp, sha256
95ed8741b355ce22, retrieved 2026-10-15, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# SN74LS273N
**lingxingic** · Flip Flops · DIP-20
SN74LS273N from lingxingic, in a DIP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | MR | input | Active-low master reset input; when driven low, all Qn outputs go low regardless of the clock and data inputs. |
| 2 | Q0 | output | Flip-flop 0 output, which takes the state of D0 on the rising edge of CP and goes low when MR is low. |
| 3 | D0 | input | Data input to flip-flop 0, sampled on the rising edge of CP and meeting the setup and hold times stated in the datasheet. |
| 4 | D1 | input | Data input to flip-flop 1, sampled on the rising edge of CP and meeting the setup and hold times stated in the datasheet. |
| 5 | Q1 | output | Flip-flop 1 output, which takes the state of D1 on the rising edge of CP and goes low when MR is low. |
| 6 | Q2 | output | Flip-flop 2 output, which takes the state of D2 on the rising edge of CP and goes low when MR is low. |
| 7 | D2 | input | Data input to flip-flop 2, sampled on the rising edge of CP and meeting the setup and hold times stated in the datasheet. |
| 8 | D3 | input | Data input to flip-flop 3, sampled on the rising edge of CP and meeting the setup and hold times stated in the datasheet. |
| 9 | Q3 | output | Flip-flop 3 output, which takes the state of D3 on the rising edge of CP and goes low when MR is low. |
| 10 | GND | power_in | Ground reference, 0 V. |
| 11 | CP | input | Clock input; all eight flip-flops are triggered on its rising edge. |
| 12 | Q4 | output | Flip-flop 4 output, which takes the state of D4 on the rising edge of CP and goes low when MR is low. |
| 13 | D4 | input | Data input to flip-flop 4, sampled on the rising edge of CP and meeting the setup and hold times stated in the datasheet. |
| 14 | D5 | input | Data input to flip-flop 5, sampled on the rising edge of CP and meeting the setup and hold times stated in the datasheet. |
| 15 | Q5 | output | Flip-flop 5 output, which takes the state of D5 on the rising edge of CP and goes low when MR is low. |
| 16 | Q6 | output | Flip-flop 6 output, which takes the state of D6 on the rising edge of CP and goes low when MR is low. |
| 17 | D6 | input | Data input to flip-flop 6, sampled on the rising edge of CP and meeting the setup and hold times stated in the datasheet. |
| 18 | D7 | input | Data input to flip-flop 7, sampled on the rising edge of CP and meeting the setup and hold times stated in the datasheet. |
| 19 | Q7 | output | Flip-flop 7 output, which takes the state of D7 on the rising edge of CP and goes low when MR is low. |
| 20 | VCC | power_in | Supply voltage; recommended range 2.0 V to 6.0 V (typical 5.0 V), absolute maximum 7.0 V. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | lingxingic |
| Package | DIP-20 |
| Category | Logic |
| Pins | 20 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage | VCC | -0.5 | | 7 | V | | 8 |
| Input clamp current | IIK | -20 | | 20 | mA | VI<-0.5V 或 VI>VCC+0.5V | 8 |
| Output clamp current | IOK | -20 | | 20 | mA | VO<-0.5V 或 VO>VCC+0.5V | 8 |
| Output current | IO | -25 | | 25 | mA | -0.5V<VO<VCC+0.5V | 8 |
| Supply current | ICC | | | 50 | mA | | 8 |
| Ground current | IGND | -50 | | | mA | | 8 |
| Storage temperature | Tstg | -65 | | 150 | ℃ | | 8 |
| Total power dissipation | Ptot | | | 500 | mW | | 8 |
| Soldering temperature (DIP) | TL | | | 245 | ℃ | 10 s | 8 |
| Supply voltage | VCC | 2 | 5 | 6 | V | | 9 |
| Input voltage | VI | 0 | | | V | | 9 |
| Output voltage | VO | 0 | | | V | | 9 |
| Input rise and fall rate | Δt/ΔV | | | 625 | ns/V | VCC=2.0V | 9 |
| Input rise and fall rate | Δt/ΔV | | 1.67 | 139 | ns/V | VCC=4.5V | 9 |
| Input rise and fall rate | Δt/ΔV | | | 83 | ns/V | VCC=6.0V | 9 |
| Operating ambient temperature | Tamb | -40 | | 125 | ℃ | | 9 |
| High-level input voltage | VIH | 1.5 | 1.2 | | V | Tamb=25℃; VCC=2.0V | 9 |
| High-level input voltage | VIH | 3.15 | 2.4 | | V | Tamb=25℃; VCC=4.5V | 9 |
| High-level input voltage | VIH | 4.2 | 3.2 | | V | Tamb=25℃; VCC=6.0V | 9 |
| Low-level input voltage | VIL | | 0.8 | 0.5 | V | Tamb=25℃; VCC=2.0V | 9 |
| Low-level input voltage | VIL | | 2.1 | 1.35 | V | Tamb=25℃; VCC=4.5V | 9 |
| Low-level input voltage | VIL | | 2.8 | 1.8 | V | Tamb=25℃; VCC=6.0V | 9 |
| High-level output voltage | VOH | 1.9 | 2 | | V | Tamb=25℃; VI=VIH或VIL; IO=-20uA；VCC=2.0V | 9 |
| High-level output voltage | VOH | 4.4 | 4.5 | | V | Tamb=25℃; VI=VIH或VIL; IO=-20uA；VCC=4.5V | 9 |
| High-level output voltage | VOH | 5.9 | 6 | | V | Tamb=25℃; VI=VIH或VIL; IO=-20uA；VCC=6.0V | 9 |
| High-level output voltage | VOH | 3.98 | 4.32 | | V | Tamb=25℃; VI=VIH或VIL; IO=-4.0mA；VCC=4.5V | 9 |
| High-level output voltage | VOH | 5.48 | 5.81 | | V | Tamb=25℃; VI=VIH或VIL; IO=-5.2mA；VCC=6.0V | 9 |
| Low-level output voltage | VOL | | 0 | 0.1 | V | Tamb=25℃; VI=VIH或VIL; IO=20uA；VCC=2.0V | 9 |
| Low-level output voltage | VOL | | 0.15 | 0.26 | V | Tamb=25℃; VI=VIH或VIL; IO=4.0mA；VCC=4.5V | 9 |
| Low-level output voltage | VOL | | 0.16 | 0.26 | V | Tamb=25℃; VI=VIH或VIL; IO=5.2mA；VCC=6.0V | 9 |
| Input leakage current | II | -1 | | 1 | uA | Tamb=25℃; VI=VCC或GND; VCC=6.0V | 9 |
| Quiescent supply current | ICC | | | 8 | uA | Tamb=25℃; VI=VCC或GND; IO=0A; VCC=6.0V | 9 |
| High-level input voltage | VIH | 1.5 | | | V | Tamb=-40℃～+125℃; VCC=2.0V | 11 |
| High-level input voltage | VIH | 3.15 | | | V | Tamb=-40℃～+125℃; VCC=4.5V | 11 |
| High-level input voltage | VIH | 4.2 | | | V | Tamb=-40℃～+125℃; VCC=6.0V | 11 |
| Low-level input voltage | VIL | | | 0.5 | V | Tamb=-40℃～+125℃; VCC=2.0V | 11 |
| Low-level input voltage | VIL | | | 1.35 | V | Tamb=-40℃～+125℃; VCC=4.5V | 11 |
| Low-level input voltage | VIL | | | 1.8 | V | Tamb=-40℃～+125℃; VCC=6.0V | 11 |
| High-level output voltage | VOH | 1.9 | | | V | Tamb=-40℃～+125℃; VI=VIH或VIL; IO=-20uA；VCC=2.0V | 11 |
| High-level output voltage | VOH | 4.4 | | | V | Tamb=-40℃～+125℃; VI=VIH或VIL; IO=-20uA；VCC=4.5V | 11 |
| High-level output voltage | VOH | 5.9 | | | V | Tamb=-40℃～+125℃; VI=VIH或VIL; IO=-20uA；VCC=6.0V | 11 |
| High-level output voltage | VOH | 3.7 | | | V | Tamb=-40℃～+125℃; VI=VIH或VIL; IO=-4.0mA；VCC=4.5V | 11 |
| High-level output voltage | VOH | 5.2 | | | V | Tamb=-40℃～+125℃; VI=VIH或VIL; IO=-5.2mA；VCC=6.0V | 11 |
| Low-level output voltage | VOL | | | 0.1 | V | Tamb=-40℃～+125℃; VI=VIH或VIL; IO=20uA；VCC=2.0V | 11 |
| Low-level output voltage | VOL | | | 0.4 | V | Tamb=-40℃～+125℃; VI=VIH或VIL; IO=4.0mA；VCC=4.5V | 11 |
| Input leakage current | II | -1 | | 1 | uA | Tamb=-40℃～+125℃; VI=VCC或GND; VCC=6.0V | 11 |
| Quiescent supply current | ICC | | | 160 | uA | Tamb=-40℃～+125℃; VI=VCC或GND; IO=0A; VCC=6.0V | 11 |
## CAD (KiCad official)
- Symbol: `SN74LS273N`
- Footprint: `Package_DIP:DIP-20_W7.62mm`
- 3D model: DIP-20 (KiCad packages3D, STEP)
- 3D model files: `sn74ls273n-etched.step` / `sn74ls273n-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `sn74ls273n.step` / `sn74ls273n.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [lingxingic datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8590921177575600128) (21 pp, sha256 `95ed8741b355ce22`, retrieved 2026-10-15, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/sn74ls273n-datasheet.pdf)