component
SN74LS273DW
Public Made by Adomby adom
Texas Instruments Flip Flops, SOIC-20-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
main
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"component": {
"mpn": "SN74LS273DW",
"manufacturer": "Texas Instruments",
"package": "SOIC-20-300mil",
"pin_count": 20,
"category": "Logic ICs",
"subcategory": "Flip Flops",
"datasheet": "https://www.ti.com/cn/lit/gpn/sn74ls273",
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"distributor_links": {
"lcsc": "C206102",
"digikey": "296-26512-5-ND",
"mouser": "595-SN74LS273DW"
},
"distributor_check": {
"checked_at": "2026-10-11T15:10:37Z",
"source": "Component Ocean /api/assign-pns",
"digikey": {
"pn": "296-26512-5-ND",
"status": "found",
"lifecycle": "Obsolete"
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},
"pins": [
{
"number": "1",
"name": "CLR",
"type": "input",
"description": "Active-low direct clear input; a low level forces all Q outputs low regardless of the clock and D inputs."
},
{
"number": "2",
"name": "1Q",
"type": "output",
"description": "Flip-flop 1 output, which takes the D1 level on the positive-going clock edge and is cleared low by CLR."
},
{
"number": "3",
"name": "1D",
"type": "input",
"description": "Data input to flip-flop 1; the level must meet the 20 ns setup time before the rising clock edge and be held for 5 ns after it."
},
{
"number": "4",
"name": "2D",
"type": "input",
"description": "Data input to flip-flop 2; the level must meet the 20 ns setup time before the rising clock edge and be held for 5 ns after it."
},
{
"number": "5",
"name": "2Q",
"type": "output",
"description": "Flip-flop 2 output, which takes the D2 level on the positive-going clock edge and is cleared low by CLR."
},
{
"number": "6",
"name": "3Q",
"type": "output",
"description": "Flip-flop 3 output, which takes the D3 level on the positive-going clock edge and is cleared low by CLR."
},
{
"number": "7",
"name": "3D",
"type": "input",
"description": "Data input to flip-flop 3; the level must meet the 20 ns setup time before the rising clock edge and be held for 5 ns after it."
},
{
"number": "8",
"name": "4D",
"type": "input",
"description": "Data input to flip-flop 4; the level must meet the 20 ns setup time before the rising clock edge and be held for 5 ns after it."
},
{
"number": "9",
"name": "4Q",
"type": "output",
"description": "Flip-flop 4 output, which takes the D4 level on the positive-going clock edge and is cleared low by CLR."
},
{
"number": "10",
"name": "GND",
"type": "power_in",
"description": "Network ground terminal; all voltage values in the datasheet are referenced to this pin."
},
{
"number": "11",
"name": "CLK",
"type": "input",
"description": "Buffered clock input; the flip-flops trigger on the positive-going edge, with clock frequency specified from 0 to 30 MHz."
},
{
"number": "12",
"name": "5Q",
"type": "output",
"description": "Flip-flop 5 output, which takes the D5 level on the positive-going clock edge and is cleared low by CLR."
},
{
"number": "13",
"name": "5D",
"type": "input",
"description": "Data input to flip-flop 5; the level must meet the 20 ns setup time before the rising clock edge and be held for 5 ns after it."
},
{
"number": "14",
"name": "6D",
"type": "input",
"description": "Data input to flip-flop 6; the level must meet the 20 ns setup time before the rising clock edge and be held for 5 ns after it."
},
{
"number": "15",
"name": "6Q",
"type": "output",
"description": "Flip-flop 6 output, which takes the D6 level on the positive-going clock edge and is cleared low by CLR."
},
{
"number": "16",
"name": "7Q",
"type": "output",
"description": "Flip-flop 7 output, which takes the D7 level on the positive-going clock edge and is cleared low by CLR."
},
{
"number": "17",
"name": "7D",
"type": "input",
"description": "Data input to flip-flop 7; the level must meet the 20 ns setup time before the rising clock edge and be held for 5 ns after it."
},
{
"number": "18",
"name": "8D",
"type": "input",
"description": "Data input to flip-flop 8; the level must meet the 20 ns setup time before the rising clock edge and be held for 5 ns after it."
},
{
"number": "19",
"name": "8Q",
"type": "output",
"description": "Flip-flop 8 output, which takes the D8 level on the positive-going clock edge and is cleared low by CLR."
},
{
"number": "20",
"name": "VCC",
"type": "power_in",
"description": "Supply voltage; recommended range is 4.75 V to 5.25 V for the SN74LS273 with a 7 V absolute maximum."
}
],
"provenance": {
"extractor": "extract_pins 0.3",
"factory_chain": {
"factory": "2.0.0",
"extractor": "extract_pins 0.3",
"primary_model": "claude-haiku-5-5",
"primary_mode": "text",
"consensus_model": "claude-sonnet-5-5",
"consensus": "agreed",
"guards": "pin_guards 0.1: passed",
"guard_notes": [
"extractor flagged: Pinout is taken from the TOP VIEW of the DW/N package on page 1, cross-checked against the logic sym; Per the package option addendum (page 7), SN74LS273DW is listed as Obsolete with 'Call TI' for avail"
],
"pages_sent": 20,
"cost_usd": 0.0796,
"at": "2026-10-11T15:10:20"
},
"datasheet": {
"url": "https://www.ti.com/cn/lit/gpn/sn74ls273",
"pages": 20,
"sha256": "f1fcdda29424ef03",
"source_tier": "lcsc"
},
"cad": "KiCad official (CC-BY-SA 4.0)",
"pins": {
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"described": 20,
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"refuses_to_fabricate": true
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