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SN74LS273DW

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Texas Instruments Flip Flops, SOIC-20-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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SN74LS273DW

Texas Instruments · Flip Flops · SOIC-20-300mil

SN74LS273DW from Texas Instruments, in a SOIC-20-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CLR input Active-low direct clear input; a low level forces all Q outputs low regardless of the clock and D inputs.
2 1Q output Flip-flop 1 output, which takes the D1 level on the positive-going clock edge and is cleared low by CLR.
3 1D input Data input to flip-flop 1; the level must meet the 20 ns setup time before the rising clock edge and be held for 5 ns after it.
4 2D input Data input to flip-flop 2; the level must meet the 20 ns setup time before the rising clock edge and be held for 5 ns after it.
5 2Q output Flip-flop 2 output, which takes the D2 level on the positive-going clock edge and is cleared low by CLR.
6 3Q output Flip-flop 3 output, which takes the D3 level on the positive-going clock edge and is cleared low by CLR.
7 3D input Data input to flip-flop 3; the level must meet the 20 ns setup time before the rising clock edge and be held for 5 ns after it.
8 4D input Data input to flip-flop 4; the level must meet the 20 ns setup time before the rising clock edge and be held for 5 ns after it.
9 4Q output Flip-flop 4 output, which takes the D4 level on the positive-going clock edge and is cleared low by CLR.
10 GND power_in Network ground terminal; all voltage values in the datasheet are referenced to this pin.
11 CLK input Buffered clock input; the flip-flops trigger on the positive-going edge, with clock frequency specified from 0 to 30 MHz.
12 5Q output Flip-flop 5 output, which takes the D5 level on the positive-going clock edge and is cleared low by CLR.
13 5D input Data input to flip-flop 5; the level must meet the 20 ns setup time before the rising clock edge and be held for 5 ns after it.
14 6D input Data input to flip-flop 6; the level must meet the 20 ns setup time before the rising clock edge and be held for 5 ns after it.
15 6Q output Flip-flop 6 output, which takes the D6 level on the positive-going clock edge and is cleared low by CLR.
16 7Q output Flip-flop 7 output, which takes the D7 level on the positive-going clock edge and is cleared low by CLR.
17 7D input Data input to flip-flop 7; the level must meet the 20 ns setup time before the rising clock edge and be held for 5 ns after it.
18 8D input Data input to flip-flop 8; the level must meet the 20 ns setup time before the rising clock edge and be held for 5 ns after it.
19 8Q output Flip-flop 8 output, which takes the D8 level on the positive-going clock edge and is cleared low by CLR.
20 VCC power_in Supply voltage; recommended range is 4.75 V to 5.25 V for the SN74LS273 with a 7 V absolute maximum.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-20-300mil
Category Logic ICs
Pins 20

CAD (KiCad official)

  • Symbol: SN74LS273DW
  • Footprint: Package_SO:SOIC-20W_7.5x12.8mm_P1.27mm
  • 3D model: SOIC-20-300mil (KiCad packages3D, STEP)
  • 3D model files: sn74ls273dw-etched.step / sn74ls273dw-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74ls273dw.step / sn74ls273dw.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (20 pp, sha256 f1fcdda29424ef03, retrieved 2026-10-11, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF