component
SN74LS266DR
Public Made by Adomby adom
lingxingic Logic Gates, SOP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.
Symbol & Footprint
Schematic Symbol
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
PCB Footprint
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
Datasheet
Open in new tab ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
README
markdownSN74LS266DR
lingxingic · Logic Gates · SOP-14
SN74LS266DR from lingxingic, in a SOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1A | input | Data input 1A of XNOR gate 1; input voltage must lie between 0 V and VCC per the recommended operating conditions. |
| 2 | 1B | input | Data input 1B of XNOR gate 1; input voltage must lie between 0 V and VCC per the recommended operating conditions. |
| 3 | 1Y | output | Open-drain data output 1Y of XNOR gate 1; output current is rated at ±25 mA (absolute maximum). |
| 4 | 2Y | output | Open-drain data output 2Y of XNOR gate 2; output current is rated at ±25 mA (absolute maximum). |
| 5 | 2A | input | Data input 2A of XNOR gate 2; input voltage must lie between 0 V and VCC per the recommended operating conditions. |
| 6 | 2B | input | Data input 2B of XNOR gate 2; input voltage must lie between 0 V and VCC per the recommended operating conditions. |
| 7 | GND | power_in | Ground reference (0 V); all voltages are referenced to this pin. |
| 8 | 3A | input | Data input 3A of XNOR gate 3; input voltage must lie between 0 V and VCC per the recommended operating conditions. |
| 9 | 3B | input | Data input 3B of XNOR gate 3; input voltage must lie between 0 V and VCC per the recommended operating conditions. |
| 10 | 3Y | output | Open-drain data output 3Y of XNOR gate 3; output current is rated at ±25 mA (absolute maximum). |
| 11 | 4Y | output | Open-drain data output 4Y of XNOR gate 4; output current is rated at ±25 mA (absolute maximum). |
| 12 | 4A | input | Data input 4A of XNOR gate 4; input voltage must lie between 0 V and VCC per the recommended operating conditions. |
| 13 | 4B | input | Data input 4B of XNOR gate 4; input voltage must lie between 0 V and VCC per the recommended operating conditions. |
| 14 | VCC | power_in | Supply voltage; recommended range 2.0 V to 6.0 V (5.0 V typical), absolute maximum 7 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | lingxingic |
| Package | SOP-14 |
| Category | Logic |
| Pins | 14 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| HIGH-level input voltage | VIH | 1.5 | 1.2 | V | VCC=2.0V; Tamb=-40℃ to +85℃ | 7 | |
| HIGH-level input voltage | VIH | 3.15 | 2.4 | V | VCC=4.5V; Tamb=-40℃ to +85℃ | 7 | |
| HIGH-level input voltage | VIH | 4.2 | 3.2 | V | VCC=6.0V; Tamb=-40℃ to +85℃ | 7 | |
| LOW-level input voltage | VIL | 0.8 | 0.5 | V | VCC=2.0V; Tamb=-40℃ to +85℃ | 7 | |
| LOW-level input voltage | VIL | 2.1 | 1.35 | V | VCC=4.5V; Tamb=-40℃ to +85℃ | 7 | |
| LOW-level input voltage | VIL | 2.8 | 1.8 | V | VCC=6.0V; Tamb=-40℃ to +85℃ | 7 | |
| LOW-level output voltage | VOL | 0.002 | 0.1 | V | VCC=2.0V; IO=20uA; Tamb=-40℃ to +85℃ | 7 | |
| LOW-level output voltage | VOL | 0.001 | 0.1 | V | VCC=4.5V; IO=20uA; Tamb=-40℃ to +85℃ | 7 | |
| LOW-level output voltage | VOL | 0.17 | 0.33 | V | VCC=4.5V; IO=4.0mA; Tamb=-40℃ to +85℃ | 7 | |
| LOW-level output voltage | VOL | 0.15 | 0.33 | V | VCC=6.0V; IO=5.2mA; Tamb=-40℃ to +85℃ | 7 | |
| input leakage current | II | -1 | 1 | uA | VCC=6.0V; VI=VCC or GND; Tamb=-40℃ to +85℃ | 7 | |
| OFF-state output current | IOZ | -5 | 5 | uA | VCC=6.0V; VI=VIH or VIL; VO=VCC or GND; Tamb=-40℃ to +85℃ | 7 | |
| supply current | ICC | 10 | uA | VCC=6.0V; VI=VCC or GND; IO=0A; Tamb=-40℃ to +85℃ | 7 | ||
| HIGH-level input voltage | VIH | 1.5 | V | VCC=2.0V; Tamb=-40℃ to +125℃ | 8 | ||
| HIGH-level input voltage | VIH | 3.15 | V | VCC=4.5V; Tamb=-40℃ to +125℃ | 8 | ||
| HIGH-level input voltage | VIH | 4.2 | V | VCC=6.0V; Tamb=-40℃ to +125℃ | 8 | ||
| LOW-level input voltage | VIL | 0.5 | V | VCC=2.0V; Tamb=-40℃ to +125℃ | 8 | ||
| LOW-level input voltage | VIL | 1.35 | V | VCC=4.5V; Tamb=-40℃ to +125℃ | 8 | ||
| LOW-level input voltage | VIL | 1.8 | V | VCC=6.0V; Tamb=-40℃ to +125℃ | 8 | ||
| LOW-level output voltage | VOL | 0.1 | V | VCC=2.0V; IO=20uA; Tamb=-40℃ to +125℃ | 8 | ||
| LOW-level output voltage | VOL | 0.4 | V | VCC=4.5V; IO=4.0mA; Tamb=-40℃ to +125℃ | 8 | ||
| input leakage current | II | -1 | 1 | uA | VCC=6.0V; VI=VCC or GND; Tamb=-40℃ to +125℃ | 8 | |
| OFF-state output current | IOZ | -10 | 10 | uA | VCC=6.0V; VI=VIH or VIL; VO=VCC or GND; Tamb=-40℃ to +125℃ | 8 | |
| supply current | ICC | 20 | uA | VCC=6.0V; VI=VCC or GND; IO=0A; Tamb=-40℃ to +125℃ | 8 | ||
| propagation delay | tPLZ, tPZL | 60 | 155 | ns | VCC=2.0V; CL=50pF; see Figure 4; Tamb=-40℃ to +85℃ | 9 | |
| propagation delay | tPLZ, tPZL | 13 | 31 | ns | VCC=4.5V; CL=50pF; Tamb=-40℃ to +85℃ | 9 | |
| propagation delay | tPLZ, tPZL | 10 | 26 | ns | VCC=6.0V; CL=50pF; Tamb=-40℃ to +85℃ | 9 | |
| transition time | tTHL | 28 | 95 | ns | VCC=2.0V; CL=50pF; see Figure 4; Tamb=-40℃ to +85℃ | 9 | |
| transition time | tTHL | 8 | 19 | ns | VCC=4.5V; CL=50pF; Tamb=-40℃ to +85℃ | 9 | |
| transition time | tTHL | 6 | 16 | ns | VCC=6.0V; CL=50pF; Tamb=-40℃ to +85℃ | 9 | |
| propagation delay | tPLZ, tPZL | 135 | ns | VCC=2.0V; CL=50pF; see Figure 4; Tamb=-40℃ to +125℃ | 9 | ||
| propagation delay | tPLZ, tPZL | 27 | ns | VCC=4.5V; CL=50pF; Tamb=-40℃ to +125℃ | 9 | ||
| propagation delay | tPLZ, tPZL | 23 | ns | VCC=6.0V; CL=50pF; Tamb=-40℃ to +125℃ | 9 | ||
| transition time | tTHL | 110 | ns | VCC=2.0V; CL=50pF; see Figure 4; Tamb=-40℃ to +125℃ | 9 | ||
| transition time | tTHL | 22 | ns | VCC=4.5V; CL=50pF; Tamb=-40℃ to +125℃ | 9 | ||
| transition time | tTHL | 19 | ns | VCC=6.0V; CL=50pF; Tamb=-40℃ to +125℃ | 9 | ||
| supply voltage | VCC | -0.5 | 7 | V | 6 | ||
| supply current | ICC | 50 | mA | 6 | |||
| ground current | IGND | -50 | mA | 6 | |||
| input clamping current | IIK | -20 | 20 | mA | VI < -0.5V or VI > VCC+0.5V | 6 | |
| output clamping current | IOK | -20 | 20 | mA | VO < -0.5V or VO > VCC+0.5V | 6 | |
| output current | IO | -25 | 25 | mA | -0.5V < VO < VCC+0.5V | 6 | |
| storage temperature | Tstg | -65 | 150 | ℃ | 6 | ||
| soldering temperature | TL | 260 | ℃ | 10s, SOP/TSSOP | 6 | ||
| supply voltage | VCC | 2 | 5 | 6 | V | 6 | |
| input voltage | VI | 0 | V | 6 | |||
| output voltage | VO | 0 | V | 6 | |||
| ambient temperature | Tamb | -40 | 125 | ℃ | 6 |
CAD (KiCad official)
- Symbol:
SN74LS266DR - Footprint:
Package_SO:SOIC-14_3.9x8.7mm_P1.27mm - 3D model: SOP-14 (KiCad packages3D, STEP)
- 3D model files:
sn74ls266dr-etched.step/sn74ls266dr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);sn74ls266dr.step/sn74ls266dr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: lingxingic datasheet (15 pp, sha256
f1197e76751e2a52, retrieved 2026-10-18, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).