component
SN74LS20DR
Public Made by Adomby adom
lingxingic Logic Gates, SOP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.
Symbol & Footprint
Schematic Symbol
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
PCB Footprint
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
Datasheet
Open in new tab ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
README
markdownSN74LS20DR
lingxingic · Logic Gates · SOP-14
SN74LS20DR from lingxingic, in a SOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1A | input | Data input 1A of NAND gate 1; per the function table on page 7, output 1Y is high whenever any one of 1A, 1B, 1C or 1D is low. |
| 2 | 1B | input | Data input 1B of NAND gate 1; per the function table on page 7, output 1Y is high whenever any one of 1A, 1B, 1C or 1D is low. |
| 3 | n.c. | unconnected | Not connected (no internal connection). |
| 4 | 1C | input | Data input 1C of NAND gate 1; per the function table on page 7, output 1Y is high whenever any one of 1A, 1B, 1C or 1D is low. |
| 5 | 1D | input | Data input 1D of NAND gate 1; per the function table on page 7, output 1Y is high whenever any one of 1A, 1B, 1C or 1D is low. |
| 6 | 1Y | output | Data output of NAND gate 1; it is high when any input of gate 1 is low and low only when all four inputs are high. |
| 7 | GND | power_in | Ground (0 V) reference for the device. |
| 8 | 2Y | output | Data output of NAND gate 2; it is high when any input of gate 2 is low and low only when all four inputs are high. |
| 9 | 2A | input | Data input 2A of NAND gate 2; per the function table on page 7, output 2Y is high whenever any one of 2A, 2B, 2C or 2D is low. |
| 10 | 2B | input | Data input 2B of NAND gate 2; per the function table on page 7, output 2Y is high whenever any one of 2A, 2B, 2C or 2D is low. |
| 11 | n.c. | unconnected | Not connected (no internal connection). |
| 12 | 2C | input | Data input 2C of NAND gate 2; per the function table on page 7, output 2Y is high whenever any one of 2A, 2B, 2C or 2D is low. |
| 13 | 2D | input | Data input 2D of NAND gate 2; per the function table on page 7, output 2Y is high whenever any one of 2A, 2B, 2C or 2D is low. |
| 14 | VCC | power_in | Power supply; recommended operating range is 2.0 V to 6.0 V (page 7). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | lingxingic |
| Package | SOP-14 |
| Category | Logic |
| Pins | 14 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| High-level input voltage (VCC=2.0V, -40~+125℃) | VIH | 1.5 | V | VCC=2.0V | 10 | ||
| High-level input voltage (VCC=4.5V, -40~+125℃) | VIH | 3.15 | V | VCC=4.5V | 10 | ||
| High-level input voltage (VCC=6.0V, -40~+125℃) | VIH | 4.2 | V | VCC=6.0V | 10 | ||
| Low-level input voltage (VCC=2.0V, -40~+125℃) | VIL | 0.5 | V | VCC=2.0V | 10 | ||
| Low-level input voltage (VCC=4.5V, -40~+125℃) | VIL | 1.35 | V | VCC=4.5V | 10 | ||
| Low-level input voltage (VCC=6.0V, -40~+125℃) | VIL | 1.8 | V | VCC=6.0V | 10 | ||
| High-level output voltage (VCC=2.0V, -40~+125℃) | VOH | 1.9 | V | VI=VIH或VIL; IO=-20uA; VCC=2.0V | 10 | ||
| High-level output voltage (VCC=4.5V, -40~+125℃) | VOH | 4.4 | V | VI=VIH或VIL; IO=-20uA; VCC=4.5V | 10 | ||
| High-level output voltage (VCC=6.0V, -40~+125℃) | VOH | 5.9 | V | VI=VIH或VIL; IO=-20uA; VCC=6.0V | 10 | ||
| High-level output voltage (VCC=4.5V, -40~+125℃) | VOH | 3.7 | V | VI=VIH或VIL; IO=-4.0mA; VCC=4.5V | 10 | ||
| High-level output voltage (VCC=6.0V, -40~+125℃) | VOH | 5.2 | V | VI=VIH或VIL; IO=-5.2mA; VCC=6.0V | 10 | ||
| Low-level output voltage (VCC=2.0V, -40~+125℃) | VOL | 0.1 | V | VI=VIH或VIL; IO=20uA; VCC=2.0V | 10 | ||
| Low-level output voltage (VCC=4.5V, -40~+125℃) | VOL | 0.1 | V | VI=VIH或VIL; IO=20uA; VCC=4.5V | 10 | ||
| Low-level output voltage (VCC=6.0V, -40~+125℃) | VOL | 0.1 | V | VI=VIH或VIL; IO=20uA; VCC=6.0V | 10 | ||
| Low-level output voltage (VCC=4.5V, -40~+125℃) | VOL | 0.4 | V | VI=VIH或VIL; IO=4.0mA; VCC=4.5V | 10 | ||
| Low-level output voltage (VCC=6.0V, -40~+125℃) | VOL | 0.4 | V | VI=VIH或VIL; IO=5.2mA; VCC=6.0V | 10 | ||
| Input leakage current | II | -1 | 1 | uA | VI=VCC或GND; VCC=6.0V | 10 | |
| Quiescent supply current | ICC | 40 | uA | VI=VCC或GND; IO=0A; VCC=6.0V | 10 | ||
| Propagation delay nA, nB to nY (VCC=2.0V, -40~+125℃) | tpd | 135 | ns | 见图6; VCC=2.0V | 12 | ||
| Propagation delay nA, nB to nY (VCC=4.5V, -40~+125℃) | tpd | 27 | ns | 见图6; VCC=4.5V | 12 | ||
| Propagation delay nA, nB to nY (VCC=6.0V, -40~+125℃) | tpd | 23 | ns | 见图6; VCC=6.0V | 12 | ||
| Transition time (VCC=2.0V, -40~+125℃) | tt | 110 | ns | 见图6; VCC=2.0V | 12 | ||
| Transition time (VCC=4.5V, -40~+125℃) | tt | 22 | ns | 见图6; VCC=4.5V | 12 | ||
| Transition time (VCC=6.0V, -40~+125℃) | tt | 19 | ns | 见图6; VCC=6.0V | 12 | ||
| Supply voltage (absolute maximum) | VCC | -0.5 | 7 | V | 7 | ||
| Input clamp current | IIK | -20 | 20 | mA | VI<-0.5V 或 VI>VCC+0.5V | 7 | |
| Output clamp current | IOK | -20 | 20 | mA | VO<-0.5V 或 VO>VCC+0.5V | 7 | |
| Output current | IO | -25 | 25 | mA | -0.5V<VO<VCC+0.5V | 7 | |
| Supply current | ICC | 50 | mA | 7 | |||
| Ground current | IGND | -50 | mA | 7 | |||
| Total power dissipation | Ptot | 500 | mW | 7 | |||
| Storage temperature | Tstg | -65 | 150 | ℃ | 7 | ||
| Soldering temperature (SOP/TSSOP) | TL | 260 | ℃ | 10 s | 7 | ||
| Supply voltage | VCC | 2 | 5 | 6 | V | 7 | |
| Input voltage | VI | 0 | V | 7 | |||
| Output voltage | VO | 0 | V | 7 | |||
| Input rise and fall rate | Δt/ΔV | 625 | ns/V | VCC=2.0V | 7 | ||
| Input rise and fall rate | Δt/ΔV | 1.67 | 139 | ns/V | VCC=4.5V | 7 | |
| Input rise and fall rate | Δt/ΔV | 83 | ns/V | VCC=6.0V | 7 | ||
| Operating ambient temperature | Tamb | -40 | 125 | ℃ | 7 |
CAD (KiCad official)
- Symbol:
SN74LS20DR - Footprint:
Package_SO:SOIC-14_3.9x8.7mm_P1.27mm - 3D model: SOP-14 (KiCad packages3D, STEP)
- 3D model files:
sn74ls20dr-etched.step/sn74ls20dr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);sn74ls20dr.step/sn74ls20dr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: lingxingic datasheet (18 pp, sha256
21bef0f218dc526e, retrieved 2026-10-19, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).