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SN74LS194N

Public Made by Adom

by adom

lingxingic Shift Registers, DIP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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SN74LS194N

lingxingic · Shift Registers · DIP-16

SN74LS194N from lingxingic, in a DIP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 MR input Asynchronous master reset input, active low, which clears the register to LOW outputs.
2 DSR input Serial data input for shift right, which is loaded into Q3 on a LOW-to-HIGH CP transition when S1=H and S0=L.
3 D0 input Parallel data input 0, loaded into Q0 on a parallel load (S1=H, S0=H) at the LOW-to-HIGH CP transition.
4 D1 input Parallel data input 1, loaded into Q1 on a parallel load (S1=H, S0=H) at the LOW-to-HIGH CP transition.
5 D2 input Parallel data input 2, loaded into Q2 on a parallel load (S1=H, S0=H) at the LOW-to-HIGH CP transition.
6 D3 input Parallel data input 3, loaded into Q3 on a parallel load (S1=H, S0=H) at the LOW-to-HIGH CP transition.
7 DSL input Serial data input for shift left, which is loaded into Q0 on a LOW-to-HIGH CP transition when S1=H and S0=L.
8 GND power_in Ground (0 V) reference for all voltages.
9 S0 input Mode control input that selects the operating mode together with S1 (hold, shift left, shift right, parallel load, reset).
10 S1 input Mode control input that selects the operating mode together with S0 (hold, shift left, shift right, parallel load, reset).
11 CP input Clock input, active on the LOW-to-HIGH edge; mode control, data and serial inputs must meet set-up and hold times relative to it.
12 Q3 output Parallel register output bit 3.
13 Q2 output Parallel register output bit 2.
14 Q1 output Parallel register output bit 1.
15 Q0 output Parallel register output bit 0.
16 VCC power_in Supply voltage; recommended operating range is 2.0 V to 6.0 V with respect to GND.

Key specifications

Parameter Value
Manufacturer lingxingic
Package DIP-16
Category Logic
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
supply voltage VCC -0.5 7 V 7
supply current ICC 50 mA 7
ground current IGND -50 mA 7
input clamping current IIK -20 20 mA VI<-0.5V or VI>VCC+0.5V 7
output clamping current IOK -20 20 mA VO<-0.5V or VO>VCC+0.5V 7
output current IO -25 25 mA -0.5V<VO<VCC+0.5V 7
storage temperature Tstg -65 150 ℃ 7
soldering temperature TL 245 ℃ 10s; DIP package 7
supply voltage VCC 2 5 6 V 7
input voltage VI 0 V 7
output voltage VO 0 V 7
ambient temperature Tamb -40 125 ℃ 7
HIGH-level input voltage VIH 1.5 1.2 V VCC=2.0V; Tamb=-40℃ to +85℃ 7
HIGH-level input voltage VIH 3.15 2.4 V VCC=4.5V; Tamb=-40℃ to +85℃ 7
HIGH-level input voltage VIH 4.2 3.2 V VCC=6.0V; Tamb=-40℃ to +85℃ 7
LOW-level input voltage VIL 0.8 0.5 V VCC=2.0V; Tamb=-40℃ to +85℃ 7
LOW-level input voltage VIL 2.1 1.35 V VCC=4.5V; Tamb=-40℃ to +85℃ 7
LOW-level input voltage VIL 2.8 1.8 V VCC=6.0V; Tamb=-40℃ to +85℃ 7
HIGH-level output voltage VOH 1.9 2 V VCC=2.0V; IO=-20uA; Tamb=-40℃ to +85℃ 7
HIGH-level output voltage VOH 4.4 4.5 V VCC=4.5V; IO=-20uA; Tamb=-40℃ to +85℃ 7
HIGH-level output voltage VOH 5.9 6 V VCC=6.0V; IO=-20uA; Tamb=-40℃ to +85℃ 7
HIGH-level output voltage VOH 3.84 4.32 V VCC=4.5V; IO=-4.0mA; Tamb=-40℃ to +85℃ 7
HIGH-level output voltage VOH 5.34 5.81 V VCC=6.0V; IO=-5.2mA; Tamb=-40℃ to +85℃ 7
LOW-level output voltage VOL 0 0.1 V VCC=2.0V; IO=20uA; Tamb=-40℃ to +85℃ 7
LOW-level output voltage VOL 0 0.1 V VCC=4.5V; IO=20uA; Tamb=-40℃ to +85℃ 8
LOW-level output voltage VOL 0.15 0.33 V VCC=4.5V; IO=4.0mA; Tamb=-40℃ to +85℃ 8
LOW-level output voltage VOL 0.16 0.33 V VCC=6.0V; IO=5.2mA; Tamb=-40℃ to +85℃ 8
input leakage current II -1 1 uA VCC=6.0V; VI=VCC or GND; Tamb=-40℃ to +85℃ 8
supply current ICC 80 uA VCC=6.0V; VI=VCC or GND; IO=0A; Tamb=-40℃ to +85℃ 8
HIGH-level input voltage VIH 1.5 V VCC=2.0V; Tamb=-40℃ to +125℃ 8
HIGH-level input voltage VIH 3.15 V VCC=4.5V; Tamb=-40℃ to +125℃ 8
HIGH-level input voltage VIH 4.2 V VCC=6.0V; Tamb=-40℃ to +125℃ 8
LOW-level input voltage VIL 0.5 V VCC=2.0V; Tamb=-40℃ to +125℃ 8
LOW-level input voltage VIL 1.35 V VCC=4.5V; Tamb=-40℃ to +125℃ 8
LOW-level input voltage VIL 1.8 V VCC=6.0V; Tamb=-40℃ to +125℃ 8
HIGH-level output voltage VOH 1.9 V VCC=2.0V; IO=-20uA; Tamb=-40℃ to +125℃ 8
HIGH-level output voltage VOH 4.4 V VCC=4.5V; IO=-20uA; Tamb=-40℃ to +125℃ 8
HIGH-level output voltage VOH 5.9 V VCC=6.0V; IO=-20uA; Tamb=-40℃ to +125℃ 8
HIGH-level output voltage VOH 3.7 V VCC=4.5V; IO=-4.0mA; Tamb=-40℃ to +125℃ 8
HIGH-level output voltage VOH 5.2 V VCC=6.0V; IO=-5.2mA; Tamb=-40℃ to +125℃ 8
LOW-level output voltage VOL 0.1 V VCC=2.0V; IO=20uA; Tamb=-40℃ to +125℃ 8
LOW-level output voltage VOL 0.4 V VCC=4.5V; IO=4.0mA; Tamb=-40℃ to +125℃ 8
supply current ICC 160 uA VCC=6.0V; VI=VCC or GND; IO=0A; Tamb=-40℃ to +125℃ 8
CP to Qn propagation delay tPLH, tPHL 47 155 ns VCC=2.0V; CL=50pF; see Figure 4; Tamb=-40℃ to +85℃ 9
CP to Qn propagation delay tPLH, tPHL 17 36 ns VCC=4.5V; CL=50pF; see Figure 4; Tamb=-40℃ to +85℃ 9
CP to Qn propagation delay tPLH, tPHL 14 31 ns VCC=6.0V; CL=50pF; see Figure 4; Tamb=-40℃ to +85℃ 9
Qn propagation delay tPHL 39 175 ns VCC=2.0V; CL=50pF; see Figure 5; Tamb=-40℃ to +85℃ 9
Qn propagation delay tPHL 14 35 ns VCC=4.5V; CL=50pF; see Figure 5; Tamb=-40℃ to +85℃ 9
Qn propagation delay tPHL 11 30 ns VCC=6.0V; CL=50pF; see Figure 5; Tamb=-40℃ to +85℃ 9
transition time tTHL, tTLH 100 17 ns VCC=2.0V; CL=50pF; see Figure 5; Tamb=-40℃ to +85℃ 9
transition time tTHL, tTLH 20 6 ns VCC=4.5V; CL=50pF; see Figure 5; Tamb=-40℃ to +85℃ 9
transition time tTHL, tTLH 17 5 ns VCC=6.0V; CL=50pF; see Figure 5; Tamb=-40℃ to +85℃ 9
clock pulse width tW 100 17 ns VCC=2.0V; CL=50pF; see Figure 4; Tamb=-40℃ to +85℃ 9
clock pulse width tW 20 6 ns VCC=4.5V; CL=50pF; see Figure 4; Tamb=-40℃ to +85℃ 9
clock pulse width tW 17 5 ns VCC=6.0V; CL=50pF; see Figure 4; Tamb=-40℃ to +85℃ 9

CAD (KiCad official)

  • Symbol: SN74LS194N
  • Footprint: Package_DIP:DIP-16_W7.62mm
  • 3D model: DIP-16 (KiCad packages3D, STEP)
  • 3D model files: sn74ls194n-etched.step / sn74ls194n-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74ls194n.step / sn74ls194n.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: lingxingic datasheet (18 pp, sha256 7bab710efae4719b, retrieved 2026-10-15, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF