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SN74LS194AD
Public Made by Adomby adom
Texas Instruments Shift Registers, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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SN74LS194AD
Texas Instruments · Shift Registers · SOIC-16
SN74LS194AD from Texas Instruments, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | CLR | input | Direct overriding clear input (active low) that forces all outputs QA-QD low. |
| 2 | SR SER | input | Shift-right serial data input, entered when S0 is high and S1 is low. |
| 3 | A | input | Parallel data input A, loaded into QA when S0 and S1 are both high. |
| 4 | B | input | Parallel data input B, loaded into QB when S0 and S1 are both high. |
| 5 | C | input | Parallel data input C, loaded into QC when S0 and S1 are both high. |
| 6 | D | input | Parallel data input D, loaded into QD when S0 and S1 are both high. |
| 7 | SL SER | input | Shift-left serial data input, entered when S0 is low and S1 is high. |
| 8 | GND | power_in | Ground. |
| 9 | S0 | input | Mode control input S0; with S1 selects hold, shift right, shift left or parallel load. |
| 10 | S1 | input | Mode control input S1; with S0 selects hold, shift right, shift left or parallel load. |
| 11 | CLK | input | Clock input; positive edge-triggered, and clocking is inhibited when both S0 and S1 are low. |
| 12 | QD | output | Parallel output D (last stage of the register). |
| 13 | QC | output | Parallel output C. |
| 14 | QB | output | Parallel output B. |
| 15 | QA | output | Parallel output A (first stage of the register). |
| 16 | VCC | power_in | Positive supply voltage. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-16 |
| Category | Logic |
| Pins | 16 |
CAD (KiCad official)
- Symbol:
SN74LS194AD - Footprint:
Package_SO:SOIC-16_3.9x9.9mm_P1.27mm - 3D model: SOIC-16 (KiCad packages3D, STEP)
- 3D model files:
sn74ls194ad-etched.step/sn74ls194ad-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);sn74ls194ad.step/sn74ls194ad.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (15 pp, sha256
999e3f51dc7bddfe, retrieved 2026-10-18, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(vision), consensusclaude-opus-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# SN74LS194AD
**Texas Instruments** · Shift Registers · SOIC-16
SN74LS194AD from Texas Instruments, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | CLR | input | Direct overriding clear input (active low) that forces all outputs QA-QD low. |
| 2 | SR SER | input | Shift-right serial data input, entered when S0 is high and S1 is low. |
| 3 | A | input | Parallel data input A, loaded into QA when S0 and S1 are both high. |
| 4 | B | input | Parallel data input B, loaded into QB when S0 and S1 are both high. |
| 5 | C | input | Parallel data input C, loaded into QC when S0 and S1 are both high. |
| 6 | D | input | Parallel data input D, loaded into QD when S0 and S1 are both high. |
| 7 | SL SER | input | Shift-left serial data input, entered when S0 is low and S1 is high. |
| 8 | GND | power_in | Ground. |
| 9 | S0 | input | Mode control input S0; with S1 selects hold, shift right, shift left or parallel load. |
| 10 | S1 | input | Mode control input S1; with S0 selects hold, shift right, shift left or parallel load. |
| 11 | CLK | input | Clock input; positive edge-triggered, and clocking is inhibited when both S0 and S1 are low. |
| 12 | QD | output | Parallel output D (last stage of the register). |
| 13 | QC | output | Parallel output C. |
| 14 | QB | output | Parallel output B. |
| 15 | QA | output | Parallel output A (first stage of the register). |
| 16 | VCC | power_in | Positive supply voltage. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-16 |
| Category | Logic |
| Pins | 16 |
## CAD (KiCad official)
- Symbol: `SN74LS194AD`
- Footprint: `Package_SO:SOIC-16_3.9x9.9mm_P1.27mm`
- 3D model: SOIC-16 (KiCad packages3D, STEP)
- 3D model files: `sn74ls194ad-etched.step` / `sn74ls194ad-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `sn74ls194ad.step` / `sn74ls194ad.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Texas Instruments datasheet](docs/sn74ls194ad-datasheet.pdf) (15 pp, sha256 `999e3f51dc7bddfe`, retrieved 2026-10-18, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (vision), consensus `claude-opus-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/sn74ls194ad-datasheet.pdf)