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SN74LS193N

Public Made by Adom

by adom

lingxingic Counters, Dividers, DIP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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SN74LS193N

lingxingic · Counters, Dividers · DIP-16

SN74LS193N from lingxingic, in a DIP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 D1 input Data input 1 for the asynchronous parallel load; it is loaded into Q1 when PL is LOW.
2 Q1 output Flip-flop output 1 (counter bit 1).
3 Q0 output Flip-flop output 0 (counter bit 0).
4 CPD input Count-down clock input; the counter decrements on its LOW-to-HIGH edge while CPU is held HIGH.
5 CPU input Count-up clock input; the counter increments on its LOW-to-HIGH edge while CPD is held HIGH.
6 Q2 output Flip-flop output 2 (counter bit 2).
7 Q3 output Flip-flop output 3 (counter bit 3).
8 GND power_in Ground (0 V) reference for all voltages on the device.
9 D3 input Data input 3 for the asynchronous parallel load; it is loaded into Q3 when PL is LOW.
10 D2 input Data input 2 for the asynchronous parallel load; it is loaded into Q2 when PL is LOW.
11 PL input Asynchronous parallel load input, active LOW; while LOW it forces D0-D3 into the outputs regardless of the clock inputs.
12 TCU output Terminal count up (carry) output, active LOW; it goes LOW at count HHHH when CPU goes LOW-to-HIGH-to-LOW transition, duplicating the count-up clock.
13 TCD output Terminal count down (borrow) output, active LOW; it goes LOW at count LLLL while CPD is LOW, duplicating the count-down clock.
14 MR input Asynchronous master reset, active HIGH; a HIGH level sets Q0-Q3 LOW and overrides both clock inputs and the parallel load.
15 D0 input Data input 0 for the asynchronous parallel load; it is loaded into Q0 when PL is LOW.
16 VCC power_in Supply voltage; the datasheet recommends 2.0 V to 6.0 V (5.0 V typical) with absolute maximum 7.0 V.

Key specifications

Parameter Value
Manufacturer lingxingic
Package DIP-16
Category Logic
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
supply voltage VCC -0.5 7 V 8
input clamping current IIK -20 20 mA VI < -0.5V or VI > VCC+0.5V 8
output clamping current IOK -20 20 mA VO < -0.5V or VO > VCC+0.5V 8
output current IO -25 25 mA VO= -0.5V to (VCC+0.5V) 8
supply current ICC 50 mA 8
ground current IGND -50 mA 8
storage temperature Tstg -65 150 ℃ 8
total power dissipation Ptot 500 mW 8
soldering temperature TL 245 ℃ 10s, DIP 8
supply voltage VCC 2 5 6 V 9
input voltage VI 0 V 9
output voltage VO 0 V 9
input transition rise and fall rate Δt/ΔV 625 ns/V VCC=2.0V 9
input transition rise and fall rate Δt/ΔV 1.67 139 ns/V VCC=4.5V 9
input transition rise and fall rate Δt/ΔV 83 ns/V VCC=6.0V 9
ambient temperature Tamb -40 125 ℃ 9
HIGH-level input voltage VIH 1.5 V VCC=2.0V; Tamb=-40℃ to +125℃ 11
HIGH-level input voltage VIH 3.15 V VCC=4.5V; Tamb=-40℃ to +125℃ 11
HIGH-level input voltage VIH 4.2 V VCC=6.0V; Tamb=-40℃ to +125℃ 11
LOW-level input voltage VIL 0.5 V VCC=2.0V; Tamb=-40℃ to +125℃ 11
LOW-level input voltage VIL 1.35 V VCC=4.5V; Tamb=-40℃ to +125℃ 11
LOW-level input voltage VIL 1.8 V VCC=6.0V; Tamb=-40℃ to +125℃ 11
HIGH-level output voltage VOH 1.9 V IO=-20uA; VCC=2.0V; VI = VIH or VIL; Tamb=-40℃ to +125℃ 11
HIGH-level output voltage VOH 4.4 V IO=-20uA; VCC=4.5V; VI = VIH or VIL; Tamb=-40℃ to +125℃ 11
HIGH-level output voltage VOH 5.9 V IO=-20uA; VCC=6.0V; VI = VIH or VIL; Tamb=-40℃ to +125℃ 11
HIGH-level output voltage VOH 3.7 V IO=-4mA; VCC=4.5V; VI = VIH or VIL; Tamb=-40℃ to +125℃ 11
HIGH-level output voltage VOH 5.2 V IO=-5.2mA; VCC=6.0V; VI = VIH or VIL; Tamb=-40℃ to +125℃ 11
LOW-level output voltage VOL 0.1 V IO=20uA; VCC=2.0V; VI = VIH or VIL; Tamb=-40℃ to +125℃ 11
LOW-level output voltage VOL 0.4 V IO=4mA; VCC=4.5V; VI = VIH or VIL; Tamb=-40℃ to +125℃ 11
input leakage current II -1 1 uA VI=VCC or GND; VCC=6.0V; Tamb=-40℃ to +125℃ 11
supply current ICC 160 uA VI=VCC or GND; IO=0A; VCC=6.0V; Tamb=-40℃ to +125℃ 11
propagation delay CPU, CPD to Qn tpd 325 ns VCC=2.0V; see Figure 6; Tamb=-40℃ to +125℃ 16
propagation delay CPU, CPD to Qn tpd 65 ns VCC=4.5V; see Figure 6; Tamb=-40℃ to +125℃ 16
propagation delay CPU, CPD to Qn tpd 55 ns VCC=6.0V; see Figure 6; Tamb=-40℃ to +125℃ 16
HIGH to LOW output transition time tTHL 110 ns VCC=2.0V; see Figure 9; Tamb=-40℃ to +125℃ 17
HIGH to LOW output transition time tTHL 22 ns VCC=4.5V; see Figure 9; Tamb=-40℃ to +125℃ 17
HIGH to LOW output transition time tTHL 19 ns VCC=6.0V; see Figure 9; Tamb=-40℃ to +125℃ 17
LOW to HIGH output transition time tTLH 110 ns VCC=2.0V; see Figure 9; Tamb=-40℃ to +125℃ 17
LOW to HIGH output transition time tTLH 22 ns VCC=4.5V; see Figure 9; Tamb=-40℃ to +125℃ 17
LOW to HIGH output transition time tTLH 19 ns VCC=6.0V; see Figure 9; Tamb=-40℃ to +125℃ 17
maximum frequency fmax 2.6 MHz CPU, CPD; see Figure 6; VCC=2.0V; Tamb=-40℃ to +125℃ 17
maximum frequency fmax 13 MHz CPU, CPD; see Figure 6; VCC=4.5V; Tamb=-40℃ to +125℃ 17
maximum frequency fmax 15 MHz CPU, CPD; see Figure 6; VCC=6.0V; Tamb=-40℃ to +125℃ 17
pulse width CPU, CPD (HIGH or LOW) tW 150 ns VCC=2.0V; see Figure 6; Tamb=-40℃ to +125℃ 17
pulse width CPU, CPD (HIGH or LOW) tW 30 ns VCC=4.5V; see Figure 6; Tamb=-40℃ to +125℃ 17
pulse width CPU, CPD (HIGH or LOW) tW 26 ns VCC=6.0V; see Figure 6; Tamb=-40℃ to +125℃ 17
set-up time Dn to PL tsu 120 ns VCC=2.0V; see Figure 10; note: CPU = CPD = HIGH; Tamb=-40℃ to +125℃ 17
set-up time Dn to PL tsu 24 ns VCC=4.5V; see Figure 10; note: CPU = CPD = HIGH; Tamb=-40℃ to +125℃ 17
set-up time Dn to PL tsu 20 ns VCC=6.0V; see Figure 10; note: CPU = CPD = HIGH; Tamb=-40℃ to +125℃ 17
hold time Dn to PL th 0 ns VCC=2.0V; see Figure 10; Tamb=-40℃ to +125℃ 17
recovery time PL to CPU, CPD trec 75 ns VCC=2.0V; see Figure 8; Tamb=-40℃ to +125℃ 17
recovery time PL to CPU, CPD trec 15 ns VCC=4.5V; see Figure 8; Tamb=-40℃ to +125℃ 17
recovery time PL to CPU, CPD trec 13 ns VCC=6.0V; see Figure 8; Tamb=-40℃ to +125℃ 17

CAD (KiCad official)

  • Symbol: SN74LS193N
  • Footprint: Package_DIP:DIP-16_W7.62mm
  • 3D model: DIP-16 (KiCad packages3D, STEP)
  • 3D model files: sn74ls193n-etched.step / sn74ls193n-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74ls193n.step / sn74ls193n.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: lingxingic datasheet (24 pp, sha256 d8392524ccdb6b42, retrieved 2026-10-15, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF