component
SN74LS192N
Public Made by Adomby adom
lingxingic Counters, Dividers, DIP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
main
SN74LS192N
lingxingic · Counters, Dividers · DIP-16
SN74LS192N from lingxingic, in a DIP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | D1 | input | Parallel data input D1, loaded into flip-flop Q1 when PL is LOW. |
| 2 | Q1 | output | Flip-flop output 1 of the counter; it is forced LOW by a HIGH on MR. |
| 3 | Q0 | output | Flip-flop output 0 of the counter; it is forced LOW by a HIGH on MR. |
| 4 | CPD | input | Count-down clock input, edge triggered on the LOW-to-HIGH transition; the counter counts down when CPU is held HIGH. |
| 5 | CPU | input | Count-up clock input, edge triggered on the LOW-to-HIGH transition; the counter counts up when CPD is held HIGH. |
| 6 | Q2 | output | Flip-flop output 2 of the counter; it is forced LOW by a HIGH on MR. |
| 7 | Q3 | output | Flip-flop output 3 of the counter; it is forced LOW by a HIGH on MR. |
| 8 | GND | power_in | Ground reference (0 V) for all voltages in the datasheet. |
| 9 | D3 | input | Parallel data input D3, loaded into flip-flop Q3 when PL is LOW. |
| 10 | D2 | input | Parallel data input D2, loaded into flip-flop Q2 when PL is LOW. |
| 11 | PL | input | Asynchronous parallel load input, active LOW; it loads D0 to D3 into the counter regardless of the clock inputs. |
| 12 | TCU | output | Terminal count up (carry) output, active LOW; it goes LOW at count 15 on the next HIGH-to-LOW transition of CPU. |
| 13 | TCD | output | Terminal count down (borrow) output, active LOW; it goes LOW in the zero state when CPD goes LOW. |
| 14 | MR | input | Asynchronous master reset input, active HIGH; it sets Q0 to Q3 LOW and overrides both clock inputs. |
| 15 | D0 | input | Parallel data input D0, loaded into flip-flop Q0 when PL is LOW. |
| 16 | VCC | power_in | Supply voltage; the recommended range is 2.0 V to 6.0 V, with 5.0 V typical. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | lingxingic |
| Package | DIP-16 |
| Category | Logic |
| Pins | 16 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| supply voltage | VCC | 2 | 5 | 6 | V | 10 | |
| input voltage | VI | 0 | V | 10 | |||
| output voltage | VO | 0 | V | 10 | |||
| input transition rise and fall rate | Δt/ΔV | 625 | ns/V | VCC=2.0V | 10 | ||
| input transition rise and fall rate | Δt/ΔV | 1.67 | 139 | ns/V | VCC=4.5V | 10 | |
| input transition rise and fall rate | Δt/ΔV | 83 | ns/V | VCC=6.0V | 10 | ||
| ambient temperature | Tamb | -40 | 125 | ℃ | 10 | ||
| supply voltage | VCC | -0.5 | 7 | V | 9 | ||
| input clamping current | IIK | -20 | 20 | mA | VI < -0.5V or VI > VCC+0.5V | 9 | |
| output clamping current | IOK | -20 | 20 | mA | VO < -0.5V or VO > VCC+0.5V | 9 | |
| output current | IO | -25 | 25 | mA | VO= -0.5V to (VCC+0.5V) | 9 | |
| supply current | ICC | 50 | mA | 9 | |||
| ground current | IGND | -50 | mA | 9 | |||
| storage temperature | Tstg | -65 | 150 | ℃ | 9 | ||
| total power dissipation | Ptot | 500 | mW | 9 | |||
| soldering temperature | TL | 245 | ℃ | 10s, DIP | 9 | ||
| HIGH-level input voltage | VIH | 1.5 | 1.2 | V | Tamb=25℃; VCC=2.0V | 10 | |
| HIGH-level input voltage | VIH | 3.15 | 2.4 | V | Tamb=25℃; VCC=4.5V | 10 | |
| HIGH-level input voltage | VIH | 4.2 | 3.2 | V | Tamb=25℃; VCC=6.0V | 10 | |
| LOW-level input voltage | VIL | 0.8 | 0.5 | V | Tamb=25℃; VCC=2.0V | 10 | |
| LOW-level input voltage | VIL | 2.1 | 1.35 | V | Tamb=25℃; VCC=4.5V | 10 | |
| LOW-level input voltage | VIL | 2.8 | 1.8 | V | Tamb=25℃; VCC=6.0V | 10 | |
| HIGH-level output voltage | VOH | 1.9 | 2 | V | Tamb=25℃; VI=VIH or VIL; IO=-20uA; VCC=2.0V | 10 | |
| HIGH-level output voltage | VOH | 4.4 | 4.5 | V | Tamb=25℃; VI=VIH or VIL; IO=-20uA; VCC=4.5V | 10 | |
| HIGH-level output voltage | VOH | 5.9 | 6 | V | Tamb=25℃; VI=VIH or VIL; IO=-20uA; VCC=6.0V | 10 | |
| HIGH-level output voltage | VOH | 3.98 | 4.32 | V | Tamb=25℃; VI=VIH or VIL; IO=-4mA; VCC=4.5V | 10 | |
| HIGH-level output voltage | VOH | 5.48 | 5.81 | V | Tamb=25℃; VI=VIH or VIL; IO=-5.2mA; VCC=6.0V | 10 | |
| LOW-level output voltage | VOL | 0 | 0.1 | V | Tamb=25℃; VI=VIH or VIL; IO=20uA; VCC=2.0V | 10 | |
| LOW-level output voltage | VOL | 0.15 | 0.26 | V | Tamb=25℃; VI=VIH or VIL; IO=4mA; VCC=4.5V | 10 | |
| LOW-level output voltage | VOL | 0.16 | 0.26 | V | Tamb=25℃; VI=VIH or VIL; IO=5.2mA; VCC=6.0V | 10 | |
| input leakage current | II | -1 | 1 | uA | Tamb=25℃; VI=VCC or GND; VCC=6.0V | 10 | |
| supply current | ICC | 8 | uA | Tamb=25℃; VI=VCC or GND; IO=0A; VCC=6.0V | 10 | ||
| HIGH-level input voltage | VIH | 1.5 | V | Tamb=-40℃ to +125℃; VCC=2.0V | 12 | ||
| HIGH-level input voltage | VIH | 3.15 | V | Tamb=-40℃ to +125℃; VCC=4.5V | 12 | ||
| HIGH-level input voltage | VIH | 4.2 | V | Tamb=-40℃ to +125℃; VCC=6.0V | 12 | ||
| LOW-level input voltage | VIL | 0.5 | V | Tamb=-40℃ to +125℃; VCC=2.0V | 12 | ||
| LOW-level input voltage | VIL | 1.35 | V | Tamb=-40℃ to +125℃; VCC=4.5V | 12 | ||
| LOW-level input voltage | VIL | 1.8 | V | Tamb=-40℃ to +125℃; VCC=6.0V | 12 | ||
| HIGH-level output voltage | VOH | 1.9 | V | Tamb=-40℃ to +125℃; VI=VIH or VIL; IO=-20uA; VCC=2.0V | 12 | ||
| HIGH-level output voltage | VOH | 4.4 | V | Tamb=-40℃ to +125℃; VI=VIH or VIL; IO=-20uA; VCC=4.5V | 12 | ||
| HIGH-level output voltage | VOH | 5.9 | V | Tamb=-40℃ to +125℃; VI=VIH or VIL; IO=-20uA; VCC=6.0V | 12 | ||
| HIGH-level output voltage | VOH | 3.7 | V | Tamb=-40℃ to +125℃; VI=VIH or VIL; IO=-4mA; VCC=4.5V | 12 | ||
| HIGH-level output voltage | VOH | 5.2 | V | Tamb=-40℃ to +125℃; VI=VIH or VIL; IO=-5.2mA; VCC=6.0V | 12 | ||
| LOW-level output voltage | VOL | 0.1 | V | Tamb=-40℃ to +125℃; VI=VIH or VIL; IO=20uA; VCC=2.0V | 12 | ||
| LOW-level output voltage | VOL | 0.4 | V | Tamb=-40℃ to +125℃; VI=VIH or VIL; IO=4mA; VCC=4.5V | 12 | ||
| input leakage current | II | -1 | 1 | uA | Tamb=-40℃ to +125℃; VI=VCC or GND; VCC=6.0V | 12 | |
| supply current | ICC | 160 | uA | Tamb=-40℃ to +125℃; VI=VCC or GND; IO=0A; VCC=6.0V | 12 | ||
| propagation delay | tpd | 23 | 43 | ns | CPU, CPD to Qn; see Figure 7; VCC=4.5V; Tamb=25℃; CL=50pF | 13 | |
| maximum frequency | fmax | 20 | 36 | MHz | CPU, CPD; see Figure 7; VCC=4.5V; Tamb=25℃; CL=50pF | 14 | |
| propagation delay | tpd | 65 | ns | CPU, CPD to Qn; see Figure 7; VCC=4.5V; Tamb=-40℃ to +125℃; CL=50pF | 17 | ||
| maximum frequency | fmax | 13 | MHz | CPU, CPD; see Figure 7; VCC=4.5V; Tamb=-40℃ to +125℃; CL=50pF | 18 |
CAD (KiCad official)
- Symbol:
SN74LS192N - Footprint:
Package_DIP:DIP-16_W7.62mm - 3D model: DIP-16 (KiCad packages3D, STEP)
- 3D model files:
sn74ls192n-etched.step/sn74ls192n-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);sn74ls192n.step/sn74ls192n.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: lingxingic datasheet (25 pp, sha256
2f9790fc62cae142, retrieved 2026-10-15, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# SN74LS192N
**lingxingic** · Counters, Dividers · DIP-16
SN74LS192N from lingxingic, in a DIP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | D1 | input | Parallel data input D1, loaded into flip-flop Q1 when PL is LOW. |
| 2 | Q1 | output | Flip-flop output 1 of the counter; it is forced LOW by a HIGH on MR. |
| 3 | Q0 | output | Flip-flop output 0 of the counter; it is forced LOW by a HIGH on MR. |
| 4 | CPD | input | Count-down clock input, edge triggered on the LOW-to-HIGH transition; the counter counts down when CPU is held HIGH. |
| 5 | CPU | input | Count-up clock input, edge triggered on the LOW-to-HIGH transition; the counter counts up when CPD is held HIGH. |
| 6 | Q2 | output | Flip-flop output 2 of the counter; it is forced LOW by a HIGH on MR. |
| 7 | Q3 | output | Flip-flop output 3 of the counter; it is forced LOW by a HIGH on MR. |
| 8 | GND | power_in | Ground reference (0 V) for all voltages in the datasheet. |
| 9 | D3 | input | Parallel data input D3, loaded into flip-flop Q3 when PL is LOW. |
| 10 | D2 | input | Parallel data input D2, loaded into flip-flop Q2 when PL is LOW. |
| 11 | PL | input | Asynchronous parallel load input, active LOW; it loads D0 to D3 into the counter regardless of the clock inputs. |
| 12 | TCU | output | Terminal count up (carry) output, active LOW; it goes LOW at count 15 on the next HIGH-to-LOW transition of CPU. |
| 13 | TCD | output | Terminal count down (borrow) output, active LOW; it goes LOW in the zero state when CPD goes LOW. |
| 14 | MR | input | Asynchronous master reset input, active HIGH; it sets Q0 to Q3 LOW and overrides both clock inputs. |
| 15 | D0 | input | Parallel data input D0, loaded into flip-flop Q0 when PL is LOW. |
| 16 | VCC | power_in | Supply voltage; the recommended range is 2.0 V to 6.0 V, with 5.0 V typical. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | lingxingic |
| Package | DIP-16 |
| Category | Logic |
| Pins | 16 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| supply voltage | VCC | 2 | 5 | 6 | V | | 10 |
| input voltage | VI | 0 | | | V | | 10 |
| output voltage | VO | 0 | | | V | | 10 |
| input transition rise and fall rate | Δt/ΔV | | | 625 | ns/V | VCC=2.0V | 10 |
| input transition rise and fall rate | Δt/ΔV | | 1.67 | 139 | ns/V | VCC=4.5V | 10 |
| input transition rise and fall rate | Δt/ΔV | | | 83 | ns/V | VCC=6.0V | 10 |
| ambient temperature | Tamb | -40 | | 125 | ℃ | | 10 |
| supply voltage | VCC | -0.5 | | 7 | V | | 9 |
| input clamping current | IIK | -20 | | 20 | mA | VI < -0.5V or VI > VCC+0.5V | 9 |
| output clamping current | IOK | -20 | | 20 | mA | VO < -0.5V or VO > VCC+0.5V | 9 |
| output current | IO | -25 | | 25 | mA | VO= -0.5V to (VCC+0.5V) | 9 |
| supply current | ICC | | | 50 | mA | | 9 |
| ground current | IGND | | | -50 | mA | | 9 |
| storage temperature | Tstg | -65 | | 150 | ℃ | | 9 |
| total power dissipation | Ptot | | | 500 | mW | | 9 |
| soldering temperature | TL | | | 245 | ℃ | 10s, DIP | 9 |
| HIGH-level input voltage | VIH | 1.5 | 1.2 | | V | Tamb=25℃; VCC=2.0V | 10 |
| HIGH-level input voltage | VIH | 3.15 | 2.4 | | V | Tamb=25℃; VCC=4.5V | 10 |
| HIGH-level input voltage | VIH | 4.2 | 3.2 | | V | Tamb=25℃; VCC=6.0V | 10 |
| LOW-level input voltage | VIL | | 0.8 | 0.5 | V | Tamb=25℃; VCC=2.0V | 10 |
| LOW-level input voltage | VIL | | 2.1 | 1.35 | V | Tamb=25℃; VCC=4.5V | 10 |
| LOW-level input voltage | VIL | | 2.8 | 1.8 | V | Tamb=25℃; VCC=6.0V | 10 |
| HIGH-level output voltage | VOH | 1.9 | 2 | | V | Tamb=25℃; VI=VIH or VIL; IO=-20uA; VCC=2.0V | 10 |
| HIGH-level output voltage | VOH | 4.4 | 4.5 | | V | Tamb=25℃; VI=VIH or VIL; IO=-20uA; VCC=4.5V | 10 |
| HIGH-level output voltage | VOH | 5.9 | 6 | | V | Tamb=25℃; VI=VIH or VIL; IO=-20uA; VCC=6.0V | 10 |
| HIGH-level output voltage | VOH | 3.98 | 4.32 | | V | Tamb=25℃; VI=VIH or VIL; IO=-4mA; VCC=4.5V | 10 |
| HIGH-level output voltage | VOH | 5.48 | 5.81 | | V | Tamb=25℃; VI=VIH or VIL; IO=-5.2mA; VCC=6.0V | 10 |
| LOW-level output voltage | VOL | | 0 | 0.1 | V | Tamb=25℃; VI=VIH or VIL; IO=20uA; VCC=2.0V | 10 |
| LOW-level output voltage | VOL | | 0.15 | 0.26 | V | Tamb=25℃; VI=VIH or VIL; IO=4mA; VCC=4.5V | 10 |
| LOW-level output voltage | VOL | | 0.16 | 0.26 | V | Tamb=25℃; VI=VIH or VIL; IO=5.2mA; VCC=6.0V | 10 |
| input leakage current | II | -1 | | 1 | uA | Tamb=25℃; VI=VCC or GND; VCC=6.0V | 10 |
| supply current | ICC | | | 8 | uA | Tamb=25℃; VI=VCC or GND; IO=0A; VCC=6.0V | 10 |
| HIGH-level input voltage | VIH | 1.5 | | | V | Tamb=-40℃ to +125℃; VCC=2.0V | 12 |
| HIGH-level input voltage | VIH | 3.15 | | | V | Tamb=-40℃ to +125℃; VCC=4.5V | 12 |
| HIGH-level input voltage | VIH | 4.2 | | | V | Tamb=-40℃ to +125℃; VCC=6.0V | 12 |
| LOW-level input voltage | VIL | | | 0.5 | V | Tamb=-40℃ to +125℃; VCC=2.0V | 12 |
| LOW-level input voltage | VIL | | | 1.35 | V | Tamb=-40℃ to +125℃; VCC=4.5V | 12 |
| LOW-level input voltage | VIL | | | 1.8 | V | Tamb=-40℃ to +125℃; VCC=6.0V | 12 |
| HIGH-level output voltage | VOH | 1.9 | | | V | Tamb=-40℃ to +125℃; VI=VIH or VIL; IO=-20uA; VCC=2.0V | 12 |
| HIGH-level output voltage | VOH | 4.4 | | | V | Tamb=-40℃ to +125℃; VI=VIH or VIL; IO=-20uA; VCC=4.5V | 12 |
| HIGH-level output voltage | VOH | 5.9 | | | V | Tamb=-40℃ to +125℃; VI=VIH or VIL; IO=-20uA; VCC=6.0V | 12 |
| HIGH-level output voltage | VOH | 3.7 | | | V | Tamb=-40℃ to +125℃; VI=VIH or VIL; IO=-4mA; VCC=4.5V | 12 |
| HIGH-level output voltage | VOH | 5.2 | | | V | Tamb=-40℃ to +125℃; VI=VIH or VIL; IO=-5.2mA; VCC=6.0V | 12 |
| LOW-level output voltage | VOL | | | 0.1 | V | Tamb=-40℃ to +125℃; VI=VIH or VIL; IO=20uA; VCC=2.0V | 12 |
| LOW-level output voltage | VOL | | | 0.4 | V | Tamb=-40℃ to +125℃; VI=VIH or VIL; IO=4mA; VCC=4.5V | 12 |
| input leakage current | II | -1 | | 1 | uA | Tamb=-40℃ to +125℃; VI=VCC or GND; VCC=6.0V | 12 |
| supply current | ICC | | | 160 | uA | Tamb=-40℃ to +125℃; VI=VCC or GND; IO=0A; VCC=6.0V | 12 |
| propagation delay | tpd | | 23 | 43 | ns | CPU, CPD to Qn; see Figure 7; VCC=4.5V; Tamb=25℃; CL=50pF | 13 |
| maximum frequency | fmax | 20 | 36 | | MHz | CPU, CPD; see Figure 7; VCC=4.5V; Tamb=25℃; CL=50pF | 14 |
| propagation delay | tpd | | | 65 | ns | CPU, CPD to Qn; see Figure 7; VCC=4.5V; Tamb=-40℃ to +125℃; CL=50pF | 17 |
| maximum frequency | fmax | 13 | | | MHz | CPU, CPD; see Figure 7; VCC=4.5V; Tamb=-40℃ to +125℃; CL=50pF | 18 |
## CAD (KiCad official)
- Symbol: `SN74LS192N`
- Footprint: `Package_DIP:DIP-16_W7.62mm`
- 3D model: DIP-16 (KiCad packages3D, STEP)
- 3D model files: `sn74ls192n-etched.step` / `sn74ls192n-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `sn74ls192n.step` / `sn74ls192n.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [lingxingic datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8603393141659881472) (25 pp, sha256 `2f9790fc62cae142`, retrieved 2026-10-15, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/sn74ls192n-datasheet.pdf)