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SN74LS175N

Public Made by Adom

by adom

lingxingic Flip Flops, DIP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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SN74LS175N

lingxingic · Flip Flops · DIP-16

SN74LS175N from lingxingic, in a DIP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 MR input Asynchronous master reset input (active LOW); when LOW it clears the flip-flops, forcing Qn LOW and the complementary output HIGH regardless of CP and Dn.
2 Q0 output Flip-flop 0 true output, which goes LOW on master reset and follows D0 on the LOW-to-HIGH clock transition per the function table.
3 ~{Q0} output Flip-flop 0 complementary output, which is the inverse of Q0 per the function table.
4 D0 input Data input for flip-flop 0, sampled on the LOW-to-HIGH transition of CP.
5 D1 input Data input for flip-flop 1, sampled on the LOW-to-HIGH transition of CP.
6 ~{Q1} output Flip-flop 1 complementary output, which is the inverse of Q1 per the function table.
7 Q1 output Flip-flop 1 true output, which goes LOW on master reset and follows D1 on the LOW-to-HIGH clock transition per the function table.
8 GND power_in Ground (0V) reference for all voltages.
9 CP input Clock input, with flip-flops triggered on the LOW-to-HIGH edge.
10 Q2 output Flip-flop 2 true output, which goes LOW on master reset and follows D2 on the LOW-to-HIGH clock transition per the function table.
11 ~{Q2} output Flip-flop 2 complementary output, which is the inverse of Q2 per the function table.
12 D2 input Data input for flip-flop 2, sampled on the LOW-to-HIGH transition of CP.
13 D3 input Data input for flip-flop 3, sampled on the LOW-to-HIGH transition of CP.
14 ~{Q3} output Flip-flop 3 complementary output, which is the inverse of Q3 per the function table.
15 Q3 output Flip-flop 3 true output, which goes LOW on master reset and follows D3 on the LOW-to-HIGH clock transition per the function table.
16 VCC power_in Positive supply voltage; the datasheet gives a recommended range of 2.0 V to 6.0 V (typ. 5.0 V).

Key specifications

Parameter Value
Manufacturer lingxingic
Package DIP-16
Category Logic
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
supply voltage VCC -0.5 7 V 9
input clamping current IIK 20 mA VI<-0.5V or VI>VCC+0.5V 9
output clamping current IOK -20 20 mA VO<-0.5V or VO>VCC+0.5V 9
output current IO -25 25 mA VO=-0.5V to (VCC+0.5V) 9
supply current ICC 50 mA 9
ground current IGND -50 mA 9
storage temperature Tstg -65 150 ℃ 9
total power dissipation Ptot 500 mW 9
soldering temperature (DIP package) TL 245 ℃ 10s, DIP 9
supply voltage VCC 2 5 6 V 9
input voltage VI 0 V 9
output voltage VO 0 V 9
ambient temperature Tamb -40 125 ℃ 9
HIGH-level input voltage VIH 1.5 V Tamb=-40℃ to +125℃; VCC=2.0V 12
HIGH-level input voltage VIH 3.15 V Tamb=-40℃ to +125℃; VCC=4.5V 12
HIGH-level input voltage VIH 4.2 V Tamb=-40℃ to +125℃; VCC=6.0V 12
LOW-level input voltage VIL 0.5 V Tamb=-40℃ to +125℃; VCC=2.0V 12
LOW-level input voltage VIL 1.35 V Tamb=-40℃ to +125℃; VCC=4.5V 12
LOW-level input voltage VIL 1.8 V Tamb=-40℃ to +125℃; VCC=6.0V 12
HIGH-level output voltage VOH 1.9 V Tamb=-40℃ to +125℃; VI=VIH or VIL; IO=-20uA; VCC=2.0V 12
HIGH-level output voltage VOH 4.4 V Tamb=-40℃ to +125℃; VI=VIH or VIL; IO=-20uA; VCC=4.5V 12
HIGH-level output voltage VOH 5.9 V Tamb=-40℃ to +125℃; VI=VIH or VIL; IO=-20uA; VCC=6.0V 12
HIGH-level output voltage VOH 3.7 V Tamb=-40℃ to +125℃; VI=VIH or VIL; IO=-4mA; VCC=4.5V 12
HIGH-level output voltage VOH 5.2 V Tamb=-40℃ to +125℃; VI=VIH or VIL; IO=-5.2mA; VCC=6.0V 12
LOW-level output voltage VOL 0.1 V Tamb=-40℃ to +125℃; VI=VIH or VIL; IO=20uA; VCC=2.0V 12
LOW-level output voltage VOL 0.4 V Tamb=-40℃ to +125℃; VI=VIH or VIL; IO=4mA; VCC=4.5V 12
input leakage current II -4 4 uA Tamb=-40℃ to +125℃; VI=VCC or GND; VCC=6.0V 12
supply current ICC 4 uA Tamb=-40℃ to +125℃; VI=VCC or GND; IO=0A; VCC=6.0V 12
propagation delay CP to Qn tPLH/tPHL 265 ns Tamb=-40℃ to +125℃, GND=0V, CL=50pF; VCC=2.0V; see Figure 4 15
propagation delay CP to Qn tPLH/tPHL 53 ns Tamb=-40℃ to +125℃, GND=0V, CL=50pF; VCC=4.5V; see Figure 4 15
propagation delay CP to Qn tPLH/tPHL 45 ns Tamb=-40℃ to +125℃, GND=0V, CL=50pF; VCC=6.0V; see Figure 4 15
HIGH to LOW propagation delay tPHL 225 ns Tamb=-40℃ to +125℃, GND=0V, CL=50pF; VCC=2.0V; see Figure 6 15
HIGH to LOW propagation delay tPHL 45 ns Tamb=-40℃ to +125℃, GND=0V, CL=50pF; VCC=4.5V; see Figure 6 15
HIGH to LOW propagation delay tPHL 38 ns Tamb=-40℃ to +125℃, GND=0V, CL=50pF; VCC=6.0V; see Figure 6 15
transition time tt 110 ns Tamb=-40℃ to +125℃, GND=0V, CL=50pF; Qn output; VCC=2.0V; see Figure 4 15
transition time tt 22 ns Tamb=-40℃ to +125℃, GND=0V, CL=50pF; Qn output; VCC=4.5V; see Figure 4 15
transition time tt 19 ns Tamb=-40℃ to +125℃, GND=0V, CL=50pF; Qn output; VCC=6.0V; see Figure 4 15
pulse width tW 120 ns Tamb=-40℃ to +125℃, GND=0V, CL=50pF; CP input HIGH or LOW; VCC=2.0V; see Figure 4 15
pulse width tW 24 ns Tamb=-40℃ to +125℃, GND=0V, CL=50pF; CP input HIGH or LOW; VCC=4.5V; see Figure 4 15
pulse width tW 20 ns Tamb=-40℃ to +125℃, GND=0V, CL=50pF; CPån input HIGH or LOW; VCC=6.0V; see Figure 4 15
recovery time trec 5 ns Tamb=-40℃ to +125℃, GND=0V, CL=50pF; to CP; VCC=2.0V; see Figure 6 15
set-up time tsu 120 ns Tamb=-40℃ to +125℃, GND=0V, CL=50pF; Dn to CP; VCC=2.0V; see Figure 4 15
set-up time tsu 24 ns Tamb=-40℃ to +125℃, GND=0V, CL=50pF; Dn to CP; VCC=4.5V; see Figure 4 15
set-up time tsu 20 ns Tamb=-40℃ to +125℃, GND=0V, CL=50pF; Dn to CP; VCC=6.0V; see Figure 4 15
hold time th 40 ns Tamb=-40℃ to +125℃, GND=0V, CL=50pF; Dn to CP; VCC=2.0V; see Figure 4 15
hold time th 8 ns Tamb=-40℃ to +125℃, GND=0V, CL=50pF; Dn to CP; VCC=4.5V; see Figure 4 15
hold time th 7 ns Tamb=-40℃ to +125℃, GND=0V, CL=50pF; Dn to CP; VCC=6.0V; see Figure 4 15
maximum frequency fmax 4 ns Tamb=-40℃ to +125℃, GND=0V, CL=50pF; CP input; VCC=2.0V; see Figure 4 15
maximum frequency fmax 20 ns Tamb=-40℃ to +125℃, GND=0V, CL=50pF; CP input; VCC=4.5V; see Figure 4 15
maximum frequency fmax 24 ns Tamb=-40℃ to +125℃, GND=0V, CL=50pF; CP input; VCC=6.0V; see Figure 4 15

CAD (KiCad official)

  • Symbol: SN74LS175N
  • Footprint: Package_DIP:DIP-16_W7.62mm
  • 3D model: DIP-16 (KiCad packages3D, STEP)
  • 3D model files: sn74ls175n-etched.step / sn74ls175n-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74ls175n.step / sn74ls175n.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: lingxingic datasheet (22 pp, sha256 737fe8175d2a2bd0, retrieved 2026-10-15, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF