component

SN74LS175DR

Public Made by Adom

by adom

Texas Instruments Flip Flops, SOIC-16. Pinout reviewed by a person against the datasheet, KiCad symbol/footprint/3D.

componentlogicsn74ls175drfactory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity

3D Model

Open in new tab ↗
Loads on click. Unloads only if this page sits in the background.

Symbol & Footprint

Schematic Symbol

Open full view ↗
Loads on click. Unloads only if this page sits in the background.

PCB Footprint

Open full view ↗
Loads on click. Unloads only if this page sits in the background.

Datasheet

Open in new tab ↗
Loads on click. Unloads only if this page sits in the background.
Download PDF
Contents

README

markdown

SN74LS175DR

Texas Instruments · Flip Flops · SOIC-16

SN74LS175DR from Texas Instruments, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CLR input Active-low direct clear input; when low, asynchronously forces all Q outputs low regardless of clock or data inputs.
2 1Q output True (Q) output of flip-flop 1, reflecting the state of 1D after the last positive clock edge.
3 1QN output Complementary output of flip-flop 1, the logical inverse of the 1Q output.
4 1D input Data input to flip-flop 1, transferred to the 1Q output on the positive-going edge of the clock when setup time is met.
5 2D input Data input to flip-flop 2, transferred to the 2Q output on the positive-going edge of the clock when setup time is met.
6 2QN output Complementary output of flip-flop 2, the logical inverse of the 2Q output.
7 2Q output True (Q) output of flip-flop 2, reflecting the state of 2D after the last positive clock edge.
8 GND power_in Ground supply reference pin.
9 CLK input Buffered clock input; data at the D inputs meeting setup time is transferred to the Q outputs on the positive-going edge of this clock.
10 3Q output True (Q) output of flip-flop 3, reflecting the state of 3D after the last positive clock edge.
11 3QN output Complementary output of flip-flop 3, the logical inverse of the 3Q output.
12 3D input Data input to flip-flop 3, transferred to the 3Q output on the positive-going edge of the clock when setup time is met.
13 4D input Data input to flip-flop 4, transferred to the 4Q output on the positive-going edge of the clock when setup time is met.
14 4QN output Complementary output of flip-flop 4, the logical inverse of the 4Q output.
15 4Q output True (Q) output of flip-flop 4, reflecting the state of 4D after the last positive clock edge.
16 VCC power_in Positive supply voltage pin.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-16
Category Logic
Pins 16

CAD (KiCad official)

  • Symbol: SN74LS175DR
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOIC-16 (KiCad packages3D, STEP)
  • 3D model files: sn74ls175dr-etched.step / sn74ls175dr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74ls175dr.step / sn74ls175dr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (16 pp, sha256 0b4e9eef66c47dd2, retrieved 2026-09-29, tier: manufacturer)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF