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SN74LS174DR

Public Made by Adom

by adom

lingxingic Flip Flops, SOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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SN74LS174DR

lingxingic · Flip Flops · SOP-16

SN74LS174DR from lingxingic, in a SOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 MR input Asynchronous master reset input, active LOW; when LOW it forces all Qn outputs LOW independent of CP (function table: MR = L gives Qn = L).
2 Q0 output Data output of flip-flop 0; follows D0 on the LOW-to-HIGH transition of CP and is forced LOW by MR.
3 D0 input Data input to flip-flop 0, sampled on the LOW-to-HIGH clock transition of CP (set-up and hold times apply per the AC characteristics).
4 D1 input Data input to flip-flop 1, sampled on the LOW-to-HIGH clock transition of CP (set-up and hold times apply per the AC characteristics).
5 Q1 output Data output of flip-flop 1; follows D1 on the LOW-to-HIGH transition of CP and is forced LOW by MR.
6 D2 input Data input to flip-flop 2, sampled on the LOW-to-HIGH clock transition of CP (set-up and hold times apply per the AC characteristics).
7 Q2 output Data output of flip-flop 2; follows D2 on the LOW-to-HIGH transition of CP and is forced LOW by MR.
8 GND power_in Ground (0 V) reference for all voltages.
9 CP input Clock input, positive (LOW-to-HIGH) edge-triggered; all six D flip-flops capture Dn on this edge.
10 Q3 output Data output of flip-flop 3; follows D3 on the LOW-to-HIGH transition of CP and is forced LOW by MR.
11 D3 input Data input to flip-flop 3, sampled on the LOW-to-HIGH clock transition of CP (set-up and hold times apply per the AC characteristics).
12 Q4 output Data output of flip-flop 4; follows D4 on the LOW-to-HIGH transition of CP and is forced LOW by MR.
13 D4 input Data input to flip-flop 4, sampled on the LOW-to-HIGH clock transition of CP (set-up and hold times apply per the AC characteristics).
14 D5 input Data input to flip-flop 5, sampled on the LOW-to-HIGH clock transition of CP (set-up and hold times apply per the AC characteristics).
15 Q5 output Data output of flip-flop 5; follows D5 on the LOW-to-HIGH transition of CP and is forced LOW by MR.
16 VCC power_in Supply voltage; recommended operating range 2.0 V to 6.0 V (typical 5.0 V), absolute maximum +7 V.

Key specifications

Parameter Value
Manufacturer lingxingic
Package SOP-16
Category Logic
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
supply voltage VCC -0.5 7 V 7
supply current ICC 50 mA 7
ground current IGND -50 mA 7
input clamping current IIK -20 20 mA VI < -0.5V or VI > VCC+0.5V 7
output clamping current IOK -20 20 mA VO < -0.5V or VO > VCC+0.5V 7
output current IO -25 25 mA -0.5V < VO < VCC+0.5V 7
storage temperature Tstg -65 150 ℃ 7
soldering temperature TL 260 ℃ 10s, SOP/TSSOP 7
supply voltage VCC 2 5 6 V 7
input voltage VI 0 V 7
output voltage VO 0 V 7
ambient temperature Tamb -40 125 ℃ 7
HIGH-level input voltage VIH 1.5 V Tamb=-40℃ to +125℃; VCC=2.0V 8
HIGH-level input voltage VIH 3.15 V Tamb=-40℃ to +125℃; VCC=4.5V 8
HIGH-level input voltage VIH 4.2 V Tamb=-40℃ to +125℃; VCC=6.0V 8
LOW-level input voltage VIL 0.5 V Tamb=-40℃ to +125℃; VCC=2.0V 8
LOW-level input voltage VIL 1.35 V Tamb=-40℃ to +125℃; VCC=4.5V 8
LOW-level input voltage VIL 1.8 V Tamb=-40℃ to +125℃; VCC=6.0V 8
HIGH-level output voltage VOH 1.9 V Tamb=-40℃ to +125℃; VCC=2.0V; IO=-20uA 8
HIGH-level output voltage VOH 4.4 V Tamb=-40℃ to +125℃; VCC=4.5V; IO=-20uA 8
HIGH-level output voltage VOH 5.9 V Tamb=-40℃ to +125℃; VCC=6.0V; IO=-20uA 8
HIGH-level output voltage VOH 3.7 V Tamb=-40℃ to +125℃; VCC=4.5V; IO=-4.0mA 8
HIGH-level output voltage VOH 5.2 V Tamb=-40℃ to +125℃; VCC=6.0V; IO=-5.2mA 8
LOW-level output voltage VOL 0.1 V Tamb=-40℃ to +125℃; VCC=2.0V; IO=20uA 8
LOW-level output voltage VOL 0.4 V Tamb=-40℃ to +125℃; VCC=4.5V; IO=4.0mA 8
input leakage current II -1 1 uA Tamb=-40℃ to +125℃; VCC=6.0V; VI=VCC or GND 8
supply current ICC 160 uA Tamb=-40℃ to +125℃; VCC=6.0V; VI=VCC or GND; IO=0A 8
CP to Qn propagation delay tPLH, tPHL 250 ns Tamb=-40℃ to +125℃; VCC=2.0V; CL=50pF; see Figure 4 10
CP to Qn propagation delay tPLH, tPHL 50 ns Tamb=-40℃ to +125℃; VCC=4.5V; CL=50pF; see Figure 4 10
CP to Qn propagation delay tPLH, tPHL 43 ns Tamb=-40℃ to +125℃; VCC=6.0V; CL=50pF; see Figure 4 10
MR to Qn HIGH to LOW propagation delay tPHL 225 ns Tamb=-40℃ to +125℃; VCC=2.0V; CL=50pF; see Figure 5 10
MR to Qn HIGH to LOW propagation delay tPHL 45 ns Tamb=-40℃ to +125℃; VCC=4.5V; CL=50pF; see Figure 5 10
MR to Qn HIGH to LOW propagation delay tPHL 38 ns Tamb=-40℃ to +125℃; VCC=6.0V; CL=50pF; see Figure 5 10
transition time tTHL, tTLH 110 ns Tamb=-40℃ to +125℃; VCC=2.0V; CL=50pF; see Figure 4 10
transition time tTHL, tTLH 22 ns Tamb=-40℃ to +125℃; VCC=4.5V; CL=50pF; see Figure 4 10
transition time tTHL, tTLH 19 ns Tamb=-40℃ to +125℃; VCC=6.0V; CL=50pF; see Figure 4 10
CP input HIGH or LOW pulse width tW 120 ns Tamb=-40℃ to +125℃; VCC=2.0V; CL=50pF; see Figure 4 10
CP input HIGH or LOW pulse width tW 24 ns Tamb=-40℃ to +125℃; VCC=4.5V; CL=50pF; see Figure 4 10
CP input HIGH or LOW pulse width tW 20 ns Tamb=-40℃ to +125℃; VCC=6.0V; CL=50pF; see Figure 4 10
MR input LOW pulse width 120 ns Tamb=-40℃ to +125℃; VCC=2.0V; CL=50pF; see Figure 5 10
MR input LOW pulse width 24 ns Tamb=-40℃ to +125℃; VCC=4.5V; CL=50pF; see Figure 5 10
MR input LOW pulse width 20 ns Tamb=-40℃ to +125℃; VCC=6.0V; CL=50pF; see Figure 5 10
MR to CP recovery time trec 5 ns Tamb=-40℃ to +125℃; VCC=2.0V; CL=50pF; see Figure 5 10
Dn to CP set-up time tsu 90 ns Tamb=-40℃ to +125℃; VCC=2.0V; CL=50pF; see Figure 4 10
Dn to CP set-up time tsu 18 ns Tamb=-40℃ to +125℃; VCC=4.5V; CL=50pF; see Figure 4 10
Dn to CP set-up time tsu 15 ns Tamb=-40℃ to +125℃; VCC=6.0V; CL=50pF; see Figure 4 10
Dn to CP hold time th 3 ns Tamb=-40℃ to +125℃; VCC=2.0V; CL=50pF; see Figure 4 10
maximum frequency fmax 4 MHZ Tamb=-40℃ to +125℃; VCC=2.0V; CL=50pF; see Figure 4 10
maximum frequency fmax 20 MHZ Tamb=-40℃ to +125℃; VCC=4.5V; CL=50pF; see Figure 4 10
maximum frequency fmax 24 MHZ Tamb=-40℃ to +125℃; VCC=6.0V; CL=50pF; see Figure 4 10
HIGH-level output voltage VOH 3.84 4.32 V Tamb=-40℃ to +85℃; VCC=4.5V; IO=-4.0mA 7
LOW-level output voltage VOL 0.15 0.33 V Tamb=-40℃ to +85℃; VCC=4.5V; IO=4.0mA 8
supply current ICC 80 uA Tamb=-40℃ to +85℃; VCC=6.0V; VI=VCC or GND; IO=0A 8

CAD (KiCad official)

  • Symbol: SN74LS174DR
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOP-16 (KiCad packages3D, STEP)
  • 3D model files: sn74ls174dr-etched.step / sn74ls174dr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74ls174dr.step / sn74ls174dr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: lingxingic datasheet (16 pp, sha256 e1ad81f05f5037c8, retrieved 2026-10-19, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF