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SN74LS173N

Public Made by Adom

by adom

lingxingic Flip Flops, DIP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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SN74LS173N

lingxingic · Flip Flops · DIP-16

SN74LS173N from lingxingic, in a DIP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1OE input Output enable input, active LOW, controls the 3-state outputs Q0 to Q3 together with 2OE; the outputs are high-impedance when either output enable is HIGH.
2 2OE input Output enable input, active LOW, controls the 3-state outputs Q0 to Q3 together with 1OE; the outputs are high-impedance when either output enable is HIGH.
3 Q0 tri_state 3-state flip-flop output for bit 0, which goes high-impedance (Z) when disabled by 1OE or 2OE.
4 Q1 tri_state 3-state flip-flop output for bit 1, which goes high-impedance (Z) when disabled by 1OE or 2OE.
5 Q2 tri_state 3-state flip-flop output for bit 2, which goes high-impedance (Z) when disabled by 1OE or 2OE.
6 Q3 tri_state 3-state flip-flop output for bit 3, which goes high-impedance (Z) when disabled by 1OE or 2OE.
7 CP input Clock input, triggered on the LOW-to-HIGH transition; data is loaded and stored on this edge.
8 GND power_in Ground reference, 0 V.
9 1E input Data enable input, active LOW; when LOW with MR inactive, D inputs are loaded into the register on the LOW-to-HIGH CP transition, and when HIGH the register holds its state.
10 2E input Data enable input, active LOW; when LOW with MR inactive, D inputs are loaded into the register on the LOW-to-HIGH CP transition, and when HIGH the register holds its state.
11 D3 input Data input for bit 3, sampled on the LOW-to-HIGH CP transition when the enable inputs are LOW.
12 D2 input Data input for bit 2, sampled on the LOW-to-HIGH CP transition when the enable inputs are LOW.
13 D1 input Data input for bit 1, sampled on the LOW-to-HIGH CP transition when the enable inputs are LOW.
14 D0 input Data input for bit 0, sampled on the LOW-to-HIGH CP transition when the enable inputs are LOW.
15 MR input Asynchronous master reset, active HIGH; forces all outputs Qn LOW independently of the clock.
16 VCC power_in Supply voltage; recommended range 2.0 V to 6.0 V (typical 5.0 V), with absolute maximum 7.0 V.

Key specifications

Parameter Value
Manufacturer lingxingic
Package DIP-16
Category Logic
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
supply voltage VCC 2 5 6 V 9
input voltage VI 0 V max printed as VCC 9
output voltage VO 0 V max printed as VCC 9
ambient temperature Tamb -40 125 ℃ 9
supply voltage VCC -0.5 7 V 9
input clamping current IIK -20 20 VI<-0.5V or VI>VCC+0.5V 9
output clamping current IOK -20 20 VO<-0.5V or VO>VCC+0.5V 9
output current IO -35 35 VO=-0.5V to (VCC+0.5V) 9
supply current ICC 70 9
ground current IGND -70 9
storage temperature Tstg -65 150 ℃ 9
soldering temperature (DIP) TL 245 ℃ 10s, DIP 9
HIGH-level input voltage VIH 1.5 V Tamb=-40℃ to +125℃; VCC=2.0V 10
HIGH-level input voltage VIH 3.15 V Tamb=-40℃ to +125℃; VCC=4.5V 10
HIGH-level input voltage VIH 4.2 V Tamb=-40℃ to +125℃; VCC=6.0V 10
LOW-level input voltage VIL 0.5 V Tamb=-40℃ to +125℃; VCC=2.0V 10
LOW-level input voltage VIL 1.35 V Tamb=-40℃ to +125℃; VCC=4.5V 10
LOW-level input voltage VIL 1.8 V Tamb=-40℃ to +125℃; VCC=6.0V 10
HIGH-level output voltage VOH 1.9 V Tamb=-40℃ to +125℃; VI=VIH or VIL; IO=-20uA; VCC=2.0V 10
HIGH-level output voltage VOH 4.4 V Tamb=-40℃ to +125℃; VI=VIH or VIL; IO=-20uA; VCC=4.5V 10
HIGH-level output voltage VOH 5.9 V Tamb=-40℃ to +125℃; VI=VIH or VIL; IO=-20uA; VCC=6.0V 10
LOW-level output voltage VOL 0.1 V Tamb=-40℃ to +125℃; VI=VIH or VIL; IO=20uA; VCC=2.0V 10
input leakage current II -1 1 uA Tamb=-40℃ to +125℃; VI=VCC or GND; VCC=6.0V 10
propagation delay MR to Qn (high to low) tPHL 38 ns Tamb=-40℃ to +125℃; CL=50pF; VCC=6.0V 14
enable time nOE to Qn ten 38 ns Tamb=-40℃ to +125℃; CL=50pF; VCC=6.0V 14
disable time OE to Qn tdis 38 ns Tamb=-40℃ to +125℃; CL=50pF; VCC=6.0V 14
transition time tt 15 ns Tamb=-40℃ to +125℃; CL=50pF; VCC=6.0V 14
pulse width CP HIGH or LOW tW 24 ns Tamb=-40℃ to +125℃; CL=50pF; VCC=4.5V 14
pulse width CP HIGH or LOW tW 20 ns Tamb=-40℃ to +125℃; CL=50pF; VCC=6.0V 14
set-up time Dn to CP tsu 90 ns Tamb=-40℃ to +125℃; CL=50pF; VCC=2.0V 15
set-up time Dn to CP tsu 18 ns Tamb=-40℃ to +125℃; CL=50pF; VCC=4.5V 15
set-up time Dn to CP tsu 15 ns Tamb=-40℃ to +125℃; CL=50pF; VCC=6.0V 15
maximum frequency CP fmax 4 MHz Tamb=-40℃ to +125℃; CL=50pF; VCC=2.0V 15
maximum frequency CP fmax 20 MHz Tamb=-40℃ to +125℃; CL=50pF; VCC=4.5V 15
maximum frequency CP fmax 24 MHz Tamb=-40℃ to +125℃; CL=50pF; VCC=6.0V 15

CAD (KiCad official)

  • Symbol: SN74LS173N
  • Footprint: Package_DIP:DIP-16_W7.62mm
  • 3D model: DIP-16 (KiCad packages3D, STEP)
  • 3D model files: sn74ls173n-etched.step / sn74ls173n-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74ls173n.step / sn74ls173n.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: lingxingic datasheet (24 pp, sha256 77b29ea81dd377d5, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF