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SN74LS166AN

Public Made by Adom

by adom

lingxingic Shift Registers, DIP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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SN74LS166AN

lingxingic · Shift Registers · DIP-16

SN74LS166AN from lingxingic, in a DIP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 DS input Serial data input, which is shifted into the register on the LOW-to-HIGH clock transition during serial shift operation per the function table.
2 D0 input Parallel data input, loaded into the register on a LOW-to-HIGH clock transition when PE and CE are LOW.
3 D1 input Parallel data input, loaded into the register on a LOW-to-HIGH clock transition when PE and CE are LOW.
4 D2 input Parallel data input, loaded into the register on a LOW-to-HIGH clock transition when PE and CE are LOW.
5 D3 input Parallel data input, loaded into the register on a LOW-to-HIGH clock transition when PE and CE are LOW.
6 CE input Clock enable input, active LOW; when HIGH the clock is inhibited and the register holds its state.
7 CP input Clock input; the register changes state on the LOW-to-HIGH edge transition.
8 GND power_in Ground (0V) reference for all voltages.
9 MR input Asynchronous master reset input, active LOW, which clears the register independently of the clock.
10 D4 input Parallel data input, loaded into the register on a LOW-to-HIGH clock transition when PE and CE are LOW.
11 D5 input Parallel data input, loaded into the register on a LOW-to-HIGH clock transition when PE and CE are LOW.
12 D6 input Parallel data input, loaded into the register on a LOW-to-HIGH clock transition when PE and CE are LOW.
13 Q7 output Serial output from the last stage of the shift register.
14 D7 input Parallel data input, loaded into the register on a LOW-to-HIGH clock transition when PE and CE are LOW.
15 PE input Parallel enable input, active LOW; selects parallel load of D0 to D7 on the clock edge.
16 VCC power_in Supply voltage; recommended operating range is 2.0 V to 6.0 V (typical 5.0 V) referenced to GND.

Key specifications

Parameter Value
Manufacturer lingxingic
Package DIP-16
Category Logic
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
supply voltage VCC -0.5 7 V 8
supply current ICC 50 mA 8
ground current IGND -50 mA 8
input clamping current IIK -20 20 mA VI < -0.5V or VI > VCC+0.5V 8
output clamping current IOK -20 20 mA VO < -0.5V or VO > VCC+0.5V 8
output current IO -25 25 mA -0.5V < VO < VCC+0.5V 8
storage temperature Tstg -65 150 ℃ 8
supply voltage VCC 2 5 6 V 8
ambient temperature Tamb -40 125 ℃ 8
HIGH-level input voltage VIH 1.5 V Tamb=-40℃ to +125℃; VCC=2.0V 10
HIGH-level input voltage VIH 3.15 V Tamb=-40℃ to +125℃; VCC=4.5V 10
HIGH-level input voltage VIH 4.2 V Tamb=-40℃ to +125℃; VCC=6.0V 10
LOW-level input voltage VIL 0.5 V Tamb=-40℃ to +125℃; VCC=2.0V 10
LOW-level input voltage VIL 1.35 V Tamb=-40℃ to +125℃; VCC=4.5V 10
LOW-level input voltage VIL 1.8 V Tamb=-40℃ to +125℃; VCC=6.0V 10
HIGH-level output voltage VOH 1.9 V Tamb=-40℃ to +125℃; VCC=2.0V; IO=-20uA 10
HIGH-level output voltage VOH 4.4 V Tamb=-40℃ to +125℃; VCC=4.5V; IO=-20uA 10
HIGH-level output voltage VOH 5.9 V Tamb=-40℃ to +125℃; VCC=6.0V; IO=-20uA 10
HIGH-level output voltage VOH 3.7 V Tamb=-40℃ to +125℃; VCC=4.5V; IO=-4.0mA 10
HIGH-level output voltage VOH 5.2 V Tamb=-40℃ to +125℃; VCC=6.0V; IO=-5.2mA 10
LOW-level output voltage VOL 0.1 V Tamb=-40℃ to +125℃; VCC=2.0V; IO=20uA 10
LOW-level output voltage VOL 0.4 V Tamb=-40℃ to +125℃; VCC=4.5V; IO=4.0mA 10
input leakage current II -1 1 uA Tamb=-40℃ to +125℃; VCC=6.0V; VI=VCC or GND 10
supply current ICC 160 uA Tamb=-40℃ to +125℃; VCC=6.0V; VI=VCC or GND; IO=0A 10
CP to Q7 propagation delay tPLH, tPHL 225 ns Tamb=-40℃ to +125℃; VCC=2.0V; CL=50pF; see Figure 4 12
CP to Q7 propagation delay tPLH, tPHL 45 ns Tamb=-40℃ to +125℃; VCC=4.5V; CL=50pF 12
CP to Q7 propagation delay tPLH, tPHL 38 ns Tamb=-40℃ to +125℃; VCC=6.0V; CL=50pF 12
MR to Q7 propagation delay 240 ns Tamb=-40℃ to +125℃; VCC=2.0V; CL=50pF; see Figure 5 12
MR to Q7 propagation delay 48 ns Tamb=-40℃ to +125℃; VCC=4.5V; CL=50pF 12
MR to Q7 propagation delay 41 ns Tamb=-40℃ to +125℃; VCC=6.0V; CL=50pF 12
transition time tTHL, tTLH 110 ns Tamb=-40℃ to +125℃; VCC=2.0V; CL=50pF; see Figure 4 12
transition time tTHL, tTLH 22 ns Tamb=-40℃ to +125℃; VCC=4.5V; CL=50pF 12
transition time tTHL, tTLH 19 ns Tamb=-40℃ to +125℃; VCC=6.0V; CL=50pF 12
CP input HIGH or LOW pulse width tw 120 ns Tamb=-40℃ to +125℃; VCC=2.0V; CL=50pF; see Figure 4 12
CP input HIGH or LOW pulse width tw 24 ns Tamb=-40℃ to +125℃; VCC=4.5V; CL=50pF 12
CP input HIGH or LOW pulse width tw 20 ns Tamb=-40℃ to +125℃; VCC=6.0V; CL=50pF 12
MR input LOW pulse width 150 ns Tamb=-40℃ to +125℃; VCC=2.0V; CL=50pF; see Figure 5 12
MR input LOW pulse width 30 ns Tamb=-40℃ to +125℃; VCC=4.5V; CL=50pF 12
MR input LOW pulse width 26 ns Tamb=-40℃ to +125℃; VCC=6.0V; CL=50pF 12
MR to CP recovery time trec 0 ns Tamb=-40℃ to +125℃; VCC=2.0V; CL=50pF; see Figure 5 12
Dn, CE to CP set-up time tsu 120 ns Tamb=-40℃ to +125℃; VCC=2.0V; CL=50pF; see Figure 6 12
Dn, CE to CP set-up time tsu 24 ns Tamb=-40℃ to +125℃; VCC=4.5V; CL=50pF 12
Dn, CE to CP set-up time tsu 20 ns Tamb=-40℃ to +125℃; VCC=6.0V; CL=50pF 12
PE to CP set-up time 150 ns Tamb=-40℃ to +125℃; VCC=2.0V; CL=50pF 12
PE to CP set-up time 30 ns Tamb=-40℃ to +125℃; VCC=4.5V; CL=50pF 12
PE to CP set-up time 26 ns Tamb=-40℃ to +125℃; VCC=6.0V; CL=50pF 12
Dn, CE to CP hold time th 2 ns Tamb=-40℃ to +125℃; VCC=2.0V; CL=50pF; see Figure 6 12
PE to CP hold time 0 ns Tamb=-40℃ to +125℃; VCC=2.0V; CL=50pF 12
maximum frequency fmax 4 MHZ Tamb=-40℃ to +125℃; VCC=2.0V; CL=50pF; see Figure 4 12
maximum frequency fmax 20 MHZ Tamb=-40℃ to +125℃; VCC=4.5V; CL=50pF 12
maximum frequency fmax 24 MHZ Tamb=-40℃ to +125℃; VCC=6.0V; CL=50pF 12

CAD (KiCad official)

  • Symbol: SN74LS166AN
  • Footprint: Package_DIP:DIP-16_W7.62mm
  • 3D model: DIP-16 (KiCad packages3D, STEP)
  • 3D model files: sn74ls166an-etched.step / sn74ls166an-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74ls166an.step / sn74ls166an.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: lingxingic datasheet (19 pp, sha256 e5ad9fd6e9d326e5, retrieved 2026-10-15, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF