component

SN74LS166ADR

Public Made by Adom

by adom

Texas Instruments Shift Registers, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentlogicsn74ls166adrfactory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity

3D Model

Open in new tab ↗
Loads on click. Unloads only if this page sits in the background.

Symbol & Footprint

Schematic Symbol

Open full view ↗
Loads on click. Unloads only if this page sits in the background.

PCB Footprint

Open full view ↗
Loads on click. Unloads only if this page sits in the background.

Datasheet

Open in new tab ↗
Loads on click. Unloads only if this page sits in the background.
Download PDF
Contents

README

markdown

SN74LS166ADR

Texas Instruments · Shift Registers · SOIC-16

SN74LS166ADR from Texas Instruments, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 SER input Serial data input, enabled when SH/LD is high and coupled into the shift register on each clock pulse.
2 A input Parallel data input A, loaded synchronously on the next clock pulse when SH/LD is low.
3 B input Parallel data input B, loaded synchronously on the next clock pulse when SH/LD is low.
4 C input Parallel data input C, loaded synchronously on the next clock pulse when SH/LD is low.
5 D input Parallel data input D, loaded synchronously on the next clock pulse when SH/LD is low.
6 CLK INH input Clock inhibit input to a two-input positive NOR gate with CLK; high inhibits clocking, and it should be changed to high only while CLK is high.
7 CLK input Clock input, advanced on the low-to-high-level edge through a NOR gate with CLK INH.
8 GND power_in Ground.
9 CLR input Active-low buffered direct clear input that overrides all other inputs, including the clock, and sets all flip-flops to zero.
10 E input Parallel data input E, loaded synchronously on the next clock pulse when SH/LD is low.
11 F input Parallel data input F, loaded synchronously on the next clock pulse when SH/LD is low.
12 G input Parallel data input G, loaded synchronously on the next clock pulse when SH/LD is low.
13 QH output Serial output from the last (eighth) stage of the shift register.
14 H input Parallel data input H, loaded synchronously on the next clock pulse when SH/LD is low.
15 SH/LD input Shift/load select input; high enables serial data input and shifting, low enables parallel inputs and synchronous loading on the next clock pulse.
16 VCC power_in Positive supply voltage.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-16
Category Logic
Pins 16

CAD (KiCad official)

  • Symbol: SN74LS166ADR
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOIC-16 (KiCad packages3D, STEP)
  • 3D model files: sn74ls166adr-etched.step / sn74ls166adr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74ls166adr.step / sn74ls166adr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (24 pp, sha256 643f0507a28f320b, retrieved 2026-10-08, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF