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SN74LS165AN

Public Made by Adom

by adom

lingxingic Shift Registers, DIP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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SN74LS165AN

lingxingic · Shift Registers · DIP-16

SN74LS165AN from lingxingic, in a DIP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PL input Asynchronous parallel load input, active low: when low, data on D0 to D7 is loaded into the shift register asynchronously, and when high, data enters serially at DS.
2 CP input Clock input, triggered on the low-to-high edge; when CE is low, data shifts on the rising edge of CP, and CE high disables CP.
3 D4 input Parallel data input (Dn) to the shift register, loaded when PL is low.
4 D5 input Parallel data input (Dn) to the shift register, loaded when PL is low.
5 D6 input Parallel data input (Dn) to the shift register, loaded when PL is low.
6 D7 input Parallel data input (Dn) to the shift register, loaded when PL is low.
7 ~{Q7} output Complementary final serial output (inverse of Q7).
8 GND power_in Ground (0 V) reference for the device.
9 Q7 output Final serial output of the 8-bit shift register.
10 DS input Serial data input, which shifts into the register on the CP clock edge when PL is high.
11 D0 input Parallel data input (Dn) to the shift register, loaded when PL is low.
12 D1 input Parallel data input (Dn) to the shift register, loaded when PL is low.
13 D2 input Parallel data input (Dn) to the shift register, loaded when PL is low.
14 D3 input Parallel data input (Dn) to the shift register, loaded when PL is low.
15 CE input Clock enable input, active low: when high, it disables the CP input.
16 VCC power_in Supply voltage; recommended range 2.0 V to 6.0 V with absolute maximum of +7 V.

Key specifications

Parameter Value
Manufacturer lingxingic
Package DIP-16
Category Logic
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Input high-level voltage VIH 1.5 V Tamb=-40℃～+125℃; VCC=2.0V 12
Input high-level voltage VIH 3.15 V Tamb=-40℃～+125℃; VCC=4.5V 12
Input high-level voltage VIH 4.2 V Tamb=-40℃～+125℃; VCC=6.0V 12
Input low-level voltage VIL 0.5 V Tamb=-40℃～+125℃; VCC=2.0V 12
Input low-level voltage VIL 1.35 V Tamb=-40℃～+125℃; VCC=4.5V 12
Input low-level voltage VIL 1.8 V Tamb=-40℃～+125℃; VCC=6.0V 12
High-level output voltage VOH 1.9 V VI=VIH or VIL; IO=-20uA; VCC=2.0V; Tamb=-40℃～+125℃ 12
High-level output voltage VOH 4.4 V VI=VIH or VIL; IO=-20uA; VCC=4.5V; Tamb=-40℃～+125℃ 12
High-level output voltage VOH 5.9 V VI=VIH or VIL; IO=-20uA; VCC=6.0V; Tamb=-40℃～+125℃ 12
High-level output voltage VOH 3.7 V VI=VIH or VIL; IO=-4.0mA; VCC=4.5V; Tamb=-40℃～+125℃ 12
High-level output voltage VOH 5.2 V VI=VIH or VIL; IO=-5.2mA; VCC=6.0V; Tamb=-40℃～+125℃ 12
Low-level output voltage VOL 0.1 V VI=VIH or VIL; IO=20uA; VCC=2.0V; Tamb=-40℃～+125℃ 12
Low-level output voltage VOL 0.4 V VI=VIH or VIL; IO=4.0mA; VCC=4.5V; Tamb=-40℃～+125℃ 12
Input leakage current II -1 1 uA VI=VCC or GND; VCC=6.0V; Tamb=-40℃～+125℃ 12
Quiescent supply current ICC 160 uA VI=VCC or GND; IO=0A; VCC=6.0V; Tamb=-40℃～+125℃ 12
Propagation delay CP/CE to Q7, Q7-bar tPLH, tPHL 250 ns Tamb=-40℃～+125℃, GND=0V, CL=50pF; VCC=2.0V; see Fig.6 15
Propagation delay CP/CE to Q7, Q7-bar tPLH, tPHL 50 ns Tamb=-40℃～+125℃, GND=0V, CL=50pF; VCC=4.5V; see Fig.6 15
Propagation delay CP/CE to Q7, Q7-bar tPLH, tPHL 43 ns Tamb=-40℃～+125℃, GND=0V, CL=50pF; VCC=6.0V; see Fig.6 15
Propagation delay PL to Q7, Q7-bar tPLH, tPHL 250 ns Tamb=-40℃～+125℃, GND=0V, CL=50pF; VCC=2.0V; see Fig.7 15
Propagation delay PL to Q7, Q7-bar tPLH, tPHL 50 ns Tamb=-40℃～+125℃, GND=0V, CL=50pF; VCC=4.5V; see Fig.7 15
Propagation delay PL to Q7, Q7-bar tPLH, tPHL 43 ns Tamb=-40℃～+125℃, GND=0V, CL=50pF; VCC=6.0V; see Fig.7 15
Propagation delay D7 to Q7, Q7-bar tPLH, tPHL 180 ns Tamb=-40℃～+125℃, GND=0V, CL=50pF; VCC=2.0V; see Fig.8 15
Propagation delay D7 to Q7, Q7-bar tPLH, tPHL 42 ns Tamb=-40℃～+125℃, GND=0V, CL=50pF; VCC=4.5V; see Fig.8 15
Propagation delay D7 to Q7, Q7-bar tPLH, tPHL 38 ns Tamb=-40℃～+125℃, GND=0V, CL=50pF; VCC=6.0V; see Fig.8 15
Clock pulse width CP high or low tW 120 ns Tamb=-40℃～+125℃, GND=0V, CL=50pF; VCC=2.0V; see Fig.6 15
Clock pulse width CP high or low tW 24 ns Tamb=-40℃～+125℃, GND=0V, CL=50pF; VCC=4.5V; see Fig.6 15
Clock pulse width CP high or low tW 20 ns Tamb=-40℃～+125℃, GND=0V, CL=50pF; VCC=6.0V; see Fig.6 15
Parallel load pulse width PL low tW 120 ns Tamb=-40℃～+125℃, GND=0V, CL=50pF; VCC=2.0V; see Fig.7 15
Parallel load pulse width PL low tW 24 ns Tamb=-40℃～+125℃, GND=0V, CL=50pF; VCC=4.5V; see Fig.7 15
Parallel load pulse width PL low tW 20 ns Tamb=-40℃～+125℃, GND=0V, CL=50pF; VCC=6.0V; see Fig.7 15
Recovery time PL to CP, CE trec 150 ns Tamb=-40℃～+125℃, GND=0V, CL=50pF; VCC=2.0V; see Fig.7 15
Recovery time PL to CP, CE trec 30 ns Tamb=-40℃～+125℃, GND=0V, CL=50pF; VCC=4.5V; see Fig.7 15
Recovery time PL to CP, CE trec 26 ns Tamb=-40℃～+125℃, GND=0V, CL=50pF; VCC=6.0V; see Fig.7 15
Setup time DS to CP, CE tsu 120 ns Tamb=-40℃～+125℃, GND=0V, CL=50pF; VCC=2.0V; see Fig.9 15
Setup time DS to CP, CE tsu 24 ns Tamb=-40℃～+125℃, GND=0V, CL=50pF; VCC=4.5V; see Fig.9 15
Setup time DS to CP, CE tsu 20 ns Tamb=-40℃～+125℃, GND=0V, CL=50pF; VCC=6.0V; see Fig.9 15
Setup time CE to CP and CP to CE tsu 120 ns Tamb=-40℃～+125℃, GND=0V, CL=50pF; VCC=2.0V; see Fig.9 15
Setup time CE to CP and CP to CE tsu 24 ns Tamb=-40℃～+125℃, GND=0V, CL=50pF; VCC=4.5V; see Fig.9 15
Setup time CE to CP and CP to CE tsu 20 ns Tamb=-40℃～+125℃, GND=0V, CL=50pF; VCC=6.0V; see Fig.9 15
Maximum clock frequency CP fmax 5 MHz Tamb=-40℃～+125℃, GND=0V, CL=50pF; VCC=2.0V; see Fig.6 15
Maximum clock frequency CP fmax 20 MHz Tamb=-40℃～+125℃, GND=0V, CL=50pF; VCC=4.5V; see Fig.6 15
Maximum clock frequency CP fmax 24 MHz Tamb=-40℃～+125℃, GND=0V, CL=50pF; VCC=6.0V; see Fig.6 15
Supply voltage VCC VCC -0.5 7 V 9
Input clamp current IIK -20 20 mA VI<-0.5V or VI>VCC+0.5V 9
Output clamp current IOK -20 20 mA VO<-0.5V or VO>VCC+0.5V 9
Output current IO -25 25 mA -0.5V<VO<VCC+0.5V 9
Supply current ICC 50 mA 9
Ground current IGND -50 mA 9
Total power dissipation Ptot 500 mW 9
Storage temperature Tstg -65 150 ℃ 9
Soldering temperature (DIP) TL 245 ℃ 10 s, DIP 9
Supply voltage VCC VCC 2 5 6 V 9
Input voltage VI VI 0 V 9
Output voltage VO VO 0 V 9
Operating ambient temperature Tamb -40 125 ℃ 9

CAD (KiCad official)

  • Symbol: SN74LS165AN
  • Footprint: Package_DIP:DIP-16_W7.62mm
  • 3D model: DIP-16 (KiCad packages3D, STEP)
  • 3D model files: sn74ls165an-etched.step / sn74ls165an-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74ls165an.step / sn74ls165an.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: lingxingic datasheet (23 pp, sha256 47ccf44c5c01b1dd, retrieved 2026-10-14, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF