SN74LS165ADR

{
 "schema": "adom.pads/1",
 "slug": "sn74ls165adr",
 "footprint": "SOIC-16_3.9x9.9mm_P1.27mm",
 "generated_from": {
  "footprint": "SOIC-16_3.9x9.9mm_P1.27mm@sha256:f9b5075740f7816c",
  "pins": "page.json:component.pins",
  "overrides": null
 },
 "pin1": {
  "pad": "1",
  "at": [
   -2.475,
   -4.445
  ],
  "corner": "top-left",
  "source": "silk-marker",
  "derived_from": "SOIC-16_3.9x9.9mm_P1.27mm@sha256:f9b5075740f7816c"
 },
 "pad_count": 16,
 "symbol_pins": [
  "1",
  "10",
  "11",
  "12",
  "13",
  "14",
  "15",
  "16",
  "2",
  "3",
  "4",
  "5",
  "6",
  "7",
  "8",
  "9"
 ],
 "paste_apertures": 0,
 "issues": [],
 "pads": [
  {
   "pad": "1",
   "kind": "smd",
   "shape": "roundrect",
   "at": [
    -2.475,
    -4.445
   ],
   "rot": 0.0,
   "size": [
    1.95,
    0.6
   ],
   "layers": [
    "F.Cu",
    "F.Mask",
    "F.Paste"
   ],
   "thermal": false,
   "pin": "1",
   "name": "SH/LD",
   "type": "input",
   "description": "Shift/Load control. Low = parallel-load data at A-H into the register (asynchronous, overrides clock). High = enable serial shifting on CLK/CLK INH. Diode-clamped TTL input, R_eq ~13 kΩ nom.",
   "is_pin1": true,
   "source": {
    "geometry": "SOIC-16_3.9x9.9mm_P1.27mm.kicad_mod",
    "meaning": "page.json:component.pins",
    "correspondence": "kicad: symbol pin number == pad name"
   }
  },
  {
   "pad": "2",
   "kind": "smd",
   "shape": "roundrect",
   "at": [
    -2.475,
    -3.175
   ],
   "rot": 0.0,
   "size": [
    1.95,
    0.6
   ],
   "layers": [
    "F.Cu",
    "F.Mask",
    "F.Paste"
   ],
   "thermal": false,
   "pin": "2",
   "name": "CLK",
   "type": "input",
   "description": "Clock input. On the rising edge (with CLK INH low and SH/LD high), data shifts from QA toward QH. CLK and CLK INH are combined in a two-input positive-NOR gate, so either may serve as clock or inhibit.",
   "is_pin1": false,
   "source": {
    "geometry": "SOIC-16_3.9x9.9mm_P1.27mm.kicad_mod",
    "meaning": "page.json:component.pins",
    "correspondence": "kicad: symbol pin number == pad name"
   }
  },
  {
   "pad": "3",
   "kind": "smd",
   "shape": "roundrect",
   "at": [
    -2.475,
    -1.905
   ],
   "rot": 0.0,
   "size": [
    1.95,
    0.6
   ],
   "layers": [
    "F.Cu",
    "F.Mask",
    "F.Paste"
   ],
   "thermal": false,
   "pin": "3",
   "name": "E",
   "type": "input",
   "description": "Parallel data input for bit E of the 8-bit word. Loaded into the corresponding stage when SH/LD is low. TTL input, R_eq ~24 kΩ nom.",
   "is_pin1": false,
   "source": {
    "geometry": "SOIC-16_3.9x9.9mm_P1.27mm.kicad_mod",
    "meaning": "page.json:component.pins",
    "correspondence": "kicad: symbol pin number == pad name"
   }
  },
  {
   "pad": "4",
   "kind": "smd",
   "shape": "roundrect",
   "at": [
    -2.475,
    -0.635
   ],
   "rot": 0.0,
   "size": [
    1.95,
    0.6
   ],
   "layers": [
    "F.Cu",
    "F.Mask",
    "F.Paste"
   ],
   "thermal": false,
   "pin": "4",
   "name": "F",
   "type": "input",
   "description": "Parallel data input for bit F of the 8-bit word. Loaded into the corresponding stage when SH/LD is low.",
   "is_pin1": false,
   "source": {
    "geometry": "SOIC-16_3.9x9.9mm_P1.27mm.kicad_mod",
    "meaning": "page.json:component.pins",
    "correspondence": "kicad: symbol pin number == pad name"
   }
  },
  {
   "pad": "5",
   "kind": "smd",
   "shape": "roundrect",
   "at": [
    -2.475,
    0.635
   ],
   "rot": 0.0,
   "size": [
    1.95,
    0.6
   ],
   "layers": [
    "F.Cu",
    "F.Mask",
    "F.Paste"
   ],
   "thermal": false,
   "pin": "5",
   "name": "G",
   "type": "input",
   "description": "Parallel data input for bit G of the 8-bit word. Loaded into the corresponding stage when SH/LD is low.",
   "is_pin1": false,
   "source": {
    "geometry": "SOIC-16_3.9x9.9mm_P1.27mm.kicad_mod",
    "meaning": "page.json:component.pins",
    "correspondence": "kicad: symbol pin number == pad name"
   }
  },
  {
   "pad": "6",
   "kind": "smd",
   "shape": "roundrect",
   "at": [
    -2.475,
    1.905
   ],
   "rot": 0.0,
   "size": [
    1.95,
    0.6
   ],
   "layers": [
    "F.Cu",
    "F.Mask",
    "F.Paste"
   ],
   "thermal": false,
   "pin": "6",
   "name": "H",
   "type": "input",
   "description": "Parallel data input for bit H (last stage) of the 8-bit word. Loaded into the QH stage when SH/LD is low; also drives the QH/QH-bar outputs directly after load.",
   "is_pin1": false,
   "source": {
    "geometry": "SOIC-16_3.9x9.9mm_P1.27mm.kicad_mod",
    "meaning": "page.json:component.pins",
    "correspondence": "kicad: symbol pin number == pad name"
   }
  },
  {
   "pad": "7",
   "kind": "smd",
   "shape": "roundrect",
   "at": [
    -2.475,
    3.175
   ],
   "rot": 0.0,
   "size": [
    1.95,
    0.6
   ],
   "layers": [
    "F.Cu",
    "F.Mask",
    "F.Paste"
   ],
   "thermal": false,
   "pin": "7",
   "name": "QH_N",
   "type": "output",
   "description": "Complementary serial output (inverted QH). Provides the inverse of the eighth-stage register bit. Totem-pole TTL output, IOH = -800 μA, IOL = 16 mA, V_OL ≤ 0.4 V.",
   "is_pin1": false,
   "source": {
    "geometry": "SOIC-16_3.9x9.9mm_P1.27mm.kicad_mod",
    "meaning": "page.json:component.pins",
    "correspondence": "kicad: symbol pin number == pad name"
   }
  },
  {
   "pad": "8",
   "kind": "smd",
   "shape": "roundrect",
   "at": [
    -2.475,
    4.445
   ],
   "rot": 0.0,
   "size": [
    1.95,
    0.6
   ],
   "layers": [
    "F.Cu",
    "F.Mask",
    "F.Paste"
   ],
   "thermal": false,
   "pin": "8",
   "name": "GND",
   "type": "power_in",
   "description": "Ground / 0 V reference for the device.",
   "is_pin1": false,
   "source": {
    "geometry": "SOIC-16_3.9x9.9mm_P1.27mm.kicad_mod",
    "meaning": "page.json:component.pins",
    "correspondence": "kicad: symbol pin number == pad name"
   }
  },
  {
   "pad": "9",
   "kind": "smd",
   "shape": "roundrect",
   "at": [
    2.475,
    4.445
   ],
   "rot": 0.0,
   "size": [
    1.95,
    0.6
   ],
   "layers": [
    "F.Cu",
    "F.Mask",
    "F.Paste"
   ],
   "thermal": false,
   "pin": "9",
   "name": "QH",
   "type": "output",
   "description": "Serial data output from the eighth register stage. During serial shift this bit is presented at QH; use as the serial-out for cascading multiple '165A devices. Totem-pole TTL output.",
   "is_pin1": false,
   "source": {
    "geometry": "SOIC-16_3.9x9.9mm_P1.27mm.kicad_mod",
    "meaning": "page.json:component.pins",
    "correspondence": "kicad: symbol pin number == pad name"
   }
  },
  {
   "pad": "10",
   "kind": "smd",
   "shape": "roundrect",
   "at": [
    2.475,
    3.175
   ],
   "rot": 0.0,
   "size": [
    1.95,
    0.6
   ],
   "layers": [
    "F.Cu",
    "F.Mask",
    "F.Paste"
   ],
   "thermal": false,
   "pin": "10",
   "name": "SER",
   "type": "input",
   "description": "Serial data input. Data at SER is shifted into the QA stage on each rising clock edge when SH/LD is high and CLK INH is low. Used to cascade '165A devices (connect prior stage's QH to next stage's SER).",
   "is_pin1": false,
   "source": {
    "geometry": "SOIC-16_3.9x9.9mm_P1.27mm.kicad_mod",
    "meaning": "page.json:component.pins",
    "correspondence": "kicad: symbol pin number == pad name"
   }
  },
  {
   "pad": "11",
   "kind": "smd",
   "shape": "roundrect",
   "at": [
    2.475,
    1.905
   ],
   "rot": 0.0,
   "size": [
    1.95,
    0.6
   ],
   "layers": [
    "F.Cu",
    "F.Mask",
    "F.Paste"
   ],
   "thermal": false,
   "pin": "11",
   "name": "A",
   "type": "input",
   "description": "Parallel data input for bit A (first stage) of the 8-bit word. Loaded into QA when SH/LD is low.",
   "is_pin1": false,
   "source": {
    "geometry": "SOIC-16_3.9x9.9mm_P1.27mm.kicad_mod",
    "meaning": "page.json:component.pins",
    "correspondence": "kicad: symbol pin number == pad name"
   }
  },
  {
   "pad": "12",
   "kind": "smd",
   "shape": "roundrect",
   "at": [
    2.475,
    0.635
   ],
   "rot": 0.0,
   "size": [
    1.95,
    0.6
   ],
   "layers": [
    "F.Cu",
    "F.Mask",
    "F.Paste"
   ],
   "thermal": false,
   "pin": "12",
   "name": "B",
   "type": "input",
   "description": "Parallel data input for bit B of the 8-bit word. Loaded when SH/LD is low.",
   "is_pin1": false,
   "source": {
    "geometry": "SOIC-16_3.9x9.9mm_P1.27mm.kicad_mod",
    "meaning": "page.json:component.pins",
    "correspondence": "kicad: symbol pin number == pad name"
   }
  },
  {
   "pad": "13",
   "kind": "smd",
   "shape": "roundrect",
   "at": [
    2.475,
    -0.635
   ],
   "rot": 0.0,
   "size": [
    1.95,
    0.6
   ],
   "layers": [
    "F.Cu",
    "F.Mask",
    "F.Paste"
   ],
   "thermal": false,
   "pin": "13",
   "name": "C",
   "type": "input",
   "description": "Parallel data input for bit C of the 8-bit word. Loaded when SH/LD is low.",
   "is_pin1": false,
   "source": {
    "geometry": "SOIC-16_3.9x9.9mm_P1.27mm.kicad_mod",
    "meaning": "page.json:component.pins",
    "correspondence": "kicad: symbol pin number == pad name"
   }
  },
  {
   "pad": "14",
   "kind": "smd",
   "shape": "roundrect",
   "at": [
    2.475,
    -1.905
   ],
   "rot": 0.0,
   "size": [
    1.95,
    0.6
   ],
   "layers": [
    "F.Cu",
    "F.Mask",
    "F.Paste"
   ],
   "thermal": false,
   "pin": "14",
   "name": "D",
   "type": "input",
   "description": "Parallel data input for bit D of the 8-bit word. Loaded when SH/LD is low.",
   "is_pin1": false,
   "source": {
    "geometry": "SOIC-16_3.9x9.9mm_P1.27mm.kicad_mod",
    "meaning": "page.json:component.pins",
    "correspondence": "kicad: symbol pin number == pad name"
   }
  },
  {
   "pad": "15",
   "kind": "smd",
   "shape": "roundrect",
   "at": [
    2.475,
    -3.175
   ],
   "rot": 0.0,
   "size": [
    1.95,
    0.6
   ],
   "layers": [
    "F.Cu",
    "F.Mask",
    "F.Paste"
   ],
   "thermal": false,
   "pin": "15",
   "name": "CLK INH",
   "type": "input",
   "description": "Clock inhibit. When high, blocks the CLK input (positive-NOR gating). Should be transitioned high only while CLK is high to avoid producing spurious clock edges.",
   "is_pin1": false,
   "source": {
    "geometry": "SOIC-16_3.9x9.9mm_P1.27mm.kicad_mod",
    "meaning": "page.json:component.pins",
    "correspondence": "kicad: symbol pin number == pad name"
   }
  },
  {
   "pad": "16",
   "kind": "smd",
   "shape": "roundrect",
   "at": [
    2.475,
    -4.445
   ],
   "rot": 0.0,
   "size": [
    1.95,
    0.6
   ],
   "layers": [
    "F.Cu",
    "F.Mask",
    "F.Paste"
   ],
   "thermal": false,
   "pin": "16",
   "name": "VCC",
   "type": "power_in",
   "description": "Positive supply, 4.75 V to 5.25 V (SN74LS165A). Typical ICC ≈ 42 mA (max 63 mA); typical power dissipation 90 mW.",
   "is_pin1": false,
   "source": {
    "geometry": "SOIC-16_3.9x9.9mm_P1.27mm.kicad_mod",
    "meaning": "page.json:component.pins",
    "correspondence": "kicad: symbol pin number == pad name"
   }
  }
 ]
}