SN74LS164DR

{
  "schema_version": 1,
  "type": "component",
  "slug": "sn74ls164dr",
  "title": "SN74LS164DR",
  "brief": "Texas Instruments Shifting Register, SOIC-14. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.",
  "version": "0.2.0",
  "license": "CC-BY-SA-4.0",
  "tags": [
    "component",
    "logic",
    "sn74ls164dr"
  ],
  "component": {
    "mpn": "SN74LS164DR",
    "manufacturer": "Texas Instruments",
    "package": "SOIC-14",
    "pin_count": 14,
    "category": "Logic",
    "subcategory": "Shifting Register",
    "datasheet": "https://www.ti.com/lit/ds/symlink/sn74ls164.pdf",
    "parts": {
      "symbol": "sn74ls164dr.kicad_sym",
      "footprint": "sn74ls164dr.kicad_mod",
      "model_3d": "sn74ls164dr-etched.glb",
      "model_3d_plain": "sn74ls164dr.glb",
      "model_3d_step": "sn74ls164dr-etched.step",
      "model_3d_step_plain": "sn74ls164dr.step",
      "lbr": "sn74ls164dr.lbr"
    },
    "distributor_links": {
      "digikey": "296-31852-2-ND",
      "mouser": "595-SN74LS164DR",
      "lcsc": "C10091"
    },
    "pins": [
      {
        "number": "1",
        "name": "A",
        "type": "input",
        "description": "Gated serial data input A. ANDed internally with serial input B to drive the first flip-flop's D input; either input held low inhibits new-data entry and forces the first stage low at the next clock edge. Diode-clamped LSTTL input, VIH >= 2 V, VIL <= 0.8 V."
      },
      {
        "number": "2",
        "name": "B",
        "type": "input",
        "description": "Gated serial data input B. ANDed internally with serial input A; a high level here enables input A to determine the next state of the first flip-flop. Diode-clamped LSTTL input."
      },
      {
        "number": "3",
        "name": "QA",
        "type": "output",
        "description": "Parallel output of shift-register stage A (first stage). Totem-pole LSTTL output, VOH >= 2.7 V @ IOH = -0.4 mA, VOL <= 0.5 V @ IOL = 8 mA."
      },
      {
        "number": "4",
        "name": "QB",
        "type": "output",
        "description": "Parallel output of shift-register stage B. Totem-pole LSTTL output."
      },
      {
        "number": "5",
        "name": "QC",
        "type": "output",
        "description": "Parallel output of shift-register stage C. Totem-pole LSTTL output."
      },
      {
        "number": "6",
        "name": "QD",
        "type": "output",
        "description": "Parallel output of shift-register stage D. Totem-pole LSTTL output."
      },
      {
        "number": "7",
        "name": "GND",
        "type": "power_in",
        "description": "Ground / 0 V reference for the device."
      },
      {
        "number": "8",
        "name": "CLK",
        "type": "input",
        "description": "Clock input. Data at the serial inputs is shifted one stage on the low-to-high transition; clock frequency 0-25 MHz (36 MHz typical). Minimum pulse width tw = 20 ns; setup 15 ns, hold 5 ns."
      },
      {
        "number": "9",
        "name": "CLR",
        "type": "input",
        "description": "Active-low asynchronous clear. Driving CLR low forces all Q outputs low independent of CLK; must be held high (with tsu(clear inactive) >= 20 ns before next clock edge) for normal shift operation."
      },
      {
        "number": "10",
        "name": "QE",
        "type": "output",
        "description": "Parallel output of shift-register stage E. Totem-pole LSTTL output."
      },
      {
        "number": "11",
        "name": "QF",
        "type": "output",
        "description": "Parallel output of shift-register stage F. Totem-pole LSTTL output."
      },
      {
        "number": "12",
        "name": "QG",
        "type": "output",
        "description": "Parallel output of shift-register stage G. Totem-pole LSTTL output."
      },
      {
        "number": "13",
        "name": "QH",
        "type": "output",
        "description": "Parallel output of shift-register stage H (last stage). Also functions as the serial output when cascading devices. Totem-pole LSTTL output."
      },
      {
        "number": "14",
        "name": "VCC",
        "type": "power_in",
        "description": "Positive supply, 4.75 V to 5.25 V (5 V nominal) for SN74LS164. Recommended bypass with 0.1 uF to GND close to the pin."
      }
    ],
    "provenance": {
      "extractor": "ds2sf",
      "datasheet": {
        "url": "https://www.ti.com/lit/ds/symlink/sn74ls164.pdf",
        "pages": 25,
        "sha256": "a1ac7a9fe0ab2158",
        "source_tier": "mfr"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 14,
        "described": 14,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
    "viewers": {
      "symbol": "viewers/symbol.html",
      "footprint": "viewers/footprint.html"
    },
    "pin1": {
      "pad": "1",
      "at": [
        -2.475,
        -3.81
      ],
      "corner": "top-left",
      "source": "silk-marker",
      "derived_from": "SOIC-14_3.9x8.7mm_P1.27mm@sha256:a885b619b22880c9",
      "mark": "drawn"
    },
    "logic": {
      "family_id": "74LS164",
      "logic_family": "74LS",
      "function_code": "164",
      "function_class": "ShiftRegister",
      "function_name": "8-Bit SIPO Shift Register",
      "manufacturer": "Texas Instruments",
      "is_specialty": false
    },
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        "role": "plain",
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        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
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          8.7,
          1.75
        ],
        "zmin_mm": 0,
        "centre_offset_mm": 0,
        "footprint_binding": "identity",
        "sha256": "3b9a775da256c8afcc28dcddfbc2eb3f266107fe61ce8446d96f2c52b6f44a70",
        "checked": "2026-10-07",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      },
      {
        "file": "sn74ls164dr-etched.step",
        "role": "eda",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
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        "zmin_mm": 0,
        "centre_offset_mm": 0,
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        "sha256": "d5d581b1840cca3b86571ff8d23b19660c40ef9c0125bc4b5448ccef1bdf95cd",
        "checked": "2026-10-19",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      }
    ]
  },
  "metadata": {
    "specs": {
      "Manufacturer": "Texas Instruments",
      "Package": "SOIC-14",
      "Category": "Logic",
      "Pins": "14"
    }
  },
  "sections": [
    "hero",
    "viewers",
    "readme",
    "breadcrumbs",
    "info"
  ],
  "discovery_triggers": [
    "sn74ls164dr"
  ],
  "discovery_pitch": "SN74LS164DR (Texas Instruments) component page with datasheet-verified CAD.",
  "author": {
    "name": "Ray"
  },
  "dependencies": {},
  "hero": {
    "type": "image",
    "path": "docs/hero.png"
  },
  "files": [
    "page.json",
    "README.md",
    "sn74ls164dr.kicad_sym",
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    "sn74ls164dr.step",
    "sn74ls164dr-etched.step",
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  "visibility": {
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  },
  "variants": [
    {
      "mpn": "SN74LS164DRD",
      "kind": "packaging"
    },
    {
      "mpn": "SN74LS164DR",
      "kind": "packaging"
    },
    {
      "mpn": "SN74LS164DRN",
      "kind": "packaging"
    },
    {
      "mpn": "SN74LS164DRJ",
      "kind": "packaging"
    },
    {
      "mpn": "SN74LS164DRW",
      "kind": "packaging"
    },
    {
      "mpn": "SN74LS164DRFK",
      "kind": "packaging"
    }
  ],
  "updated_at": "2026-09-25T07:17:08.475Z"
}