component
SN74LS163ADR
Public Made by Adomby adom
Texas Instruments Counters, Dividers, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
← Commit history
README.mdadded+52@@ -0,0 +1,52 @@+# SN74LS163ADR++**Texas Instruments** · Counters, Dividers · SOIC-16++SN74LS163ADR from Texas Instruments, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | CLR | input | Active-low clear input; on the 'LS163A the clear is synchronous and sets all four flip-flop outputs low after the next clock pulse regardless of the enable inputs. |+| 2 | CLK | input | Clock input; the buffered clock triggers the four flip-flops on the rising edge of the clock waveform. |+| 3 | A | input | Data input A, loaded synchronously into the QA flip-flop when LOAD is low. |+| 4 | B | input | Data input B, loaded synchronously into the QB flip-flop when LOAD is low. |+| 5 | C | input | Data input C, loaded synchronously into the QC flip-flop when LOAD is low. |+| 6 | D | input | Data input D, loaded synchronously into the QD flip-flop when LOAD is low. |+| 7 | ENP | input | Count-enable input P; with ENT it enables counting when both are high. |+| 8 | GND | power_in | Ground. |+| 9 | LOAD | input | Active-low synchronous load input; a low level disables the counter and loads the data inputs on the next clock pulse regardless of the enable inputs. |+| 10 | ENT | input | Count-enable input T; it also gates the ripple carry output RCO. |+| 11 | QD | output | Counter output D (most significant bit). |+| 12 | QC | output | Counter output C. |+| 13 | QB | output | Counter output B. |+| 14 | QA | output | Counter output A (least significant bit). |+| 15 | RCO | output | Ripple carry output for n-bit cascading; counting spikes may occur on this output. |+| 16 | VCC | power_in | Supply voltage. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | SOIC-16 |+| Category | Logic |+| Pins | 16 |++## CAD (KiCad official)++- Symbol: `SN74LS163ADR`+- Footprint: `Package_SO:SOIC-16_3.9x9.9mm_P1.27mm`+- 3D model: SOIC-16 (KiCad packages3D, STEP)+- 3D model files: `sn74ls163adr-etched.step` / `sn74ls163adr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `sn74ls163adr.step` / `sn74ls163adr.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/lit/ds/symlink/sn74ls163a.pdf) (40 pp, sha256 `0ea50a72dfbd95c3`, retrieved 2026-10-05, tier: manufacturer)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text+vision), consensus `claude-opus-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/sn74ls163adr-datasheet.pdf)
page.jsonadded+209@@ -0,0 +1,209 @@+{+ "slug": "sn74ls163adr",+ "version": "0.1.0",+ "type": "component",+ "description": "Texas Instruments Counters, Dividers, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "logic",+ "sn74ls163adr",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "sn74ls163adr.kicad_sym",+ "sn74ls163adr.kicad_mod",+ "sn74ls163adr.glb",+ "sn74ls163adr.step",+ "sn74ls163adr.lbr",+ "docs/hero.png",+ "docs/sn74ls163adr-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html",+ "sn74ls163adr-hero.glb",+ "sn74ls163adr-hero.overlay.json"+ ],+ "component": {+ "mpn": "SN74LS163ADR",+ "manufacturer": "Texas Instruments",+ "package": "SOIC-16",+ "pin_count": 16,+ "category": "Logic",+ "subcategory": "Counters, Dividers",+ "datasheet": "https://www.ti.com/lit/ds/symlink/sn74ls163a.pdf",+ "parts": {+ "symbol": "sn74ls163adr.kicad_sym",+ "footprint": "sn74ls163adr.kicad_mod",+ "model_3d": "sn74ls163adr-hero.glb",+ "model_3d_plain": "sn74ls163adr.glb",+ "model_3d_step": "sn74ls163adr-etched.step",+ "model_3d_step_plain": "sn74ls163adr.step",+ "lbr": "sn74ls163adr.lbr"+ },+ "distributor_links": {+ "lcsc": 2675457,+ "digikey": "296-44704-2-ND",+ "mouser": "595-SN74LS163ADR"+ },+ "distributor_check": {+ "checked_at": "2026-10-05T21:22:13Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": "296-44704-2-ND",+ "status": "found",+ "lifecycle": "Active"+ },+ "mouser": {+ "pn": "595-SN74LS163ADR",+ "status": "found"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "CLR",+ "type": "input",+ "description": "Active-low clear input; on the 'LS163A the clear is synchronous and sets all four flip-flop outputs low after the next clock pulse regardless of the enable inputs."+ },+ {+ "number": "2",+ "name": "CLK",+ "type": "input",+ "description": "Clock input; the buffered clock triggers the four flip-flops on the rising edge of the clock waveform."+ },+ {+ "number": "3",+ "name": "A",+ "type": "input",+ "description": "Data input A, loaded synchronously into the QA flip-flop when LOAD is low."+ },+ {+ "number": "4",+ "name": "B",+ "type": "input",+ "description": "Data input B, loaded synchronously into the QB flip-flop when LOAD is low."+ },+ {+ "number": "5",+ "name": "C",+ "type": "input",+ "description": "Data input C, loaded synchronously into the QC flip-flop when LOAD is low."+ },+ {+ "number": "6",+ "name": "D",+ "type": "input",+ "description": "Data input D, loaded synchronously into the QD flip-flop when LOAD is low."+ },+ {+ "number": "7",+ "name": "ENP",+ "type": "input",+ "description": "Count-enable input P; with ENT it enables counting when both are high."+ },+ {+ "number": "8",+ "name": "GND",+ "type": "power_in",+ "description": "Ground."+ },+ {+ "number": "9",+ "name": "LOAD",+ "type": "input",+ "description": "Active-low synchronous load input; a low level disables the counter and loads the data inputs on the next clock pulse regardless of the enable inputs."+ },+ {+ "number": "10",+ "name": "ENT",+ "type": "input",+ "description": "Count-enable input T; it also gates the ripple carry output RCO."+ },+ {+ "number": "11",+ "name": "QD",+ "type": "output",+ "description": "Counter output D (most significant bit)."+ },+ {+ "number": "12",+ "name": "QC",+ "type": "output",+ "description": "Counter output C."+ },+ {+ "number": "13",+ "name": "QB",+ "type": "output",+ "description": "Counter output B."+ },+ {+ "number": "14",+ "name": "QA",+ "type": "output",+ "description": "Counter output A (least significant bit)."+ },+ {+ "number": "15",+ "name": "RCO",+ "type": "output",+ "description": "Ripple carry output for n-bit cascading; counting spikes may occur on this output."+ },+ {+ "number": "16",+ "name": "VCC",+ "type": "power_in",+ "description": "Supply voltage."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-sonnet-5-5",+ "primary_mode": "text+vision",+ "consensus_model": "claude-opus-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: Pin numbers are from the D/J/N/W top-view pinout on page 1; the D package drawing itself is not in t",+ "vision extraction: provenance cannot be text-verified; needs consensus"+ ],+ "pages_sent": 40,+ "cost_usd": 0.5127,+ "at": "2026-10-05T21:21:54"+ },+ "datasheet": {+ "url": "https://www.ti.com/lit/ds/symlink/sn74ls163a.pdf",+ "pages": 40,+ "sha256": "0ea50a72dfbd95c3",+ "source_tier": "mfr"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 16,+ "described": 16,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ }+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}