component

SN74LS14N

Public Made by Adom

by adom

lingxingic Inverters, DIP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentlogicsn74ls14nfactory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity
main
Download ZIP Propose a change
Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 8d ago
viewers sn74ls14n: viewers · Ray 8d ago
package.json Publish 0.1.0 · Ray 8d ago
page.json Set visibility: public · Ray 8d ago
README.md Publish 0.1.0 · Ray 8d ago
sn74ls14n-etched.glb Publish 0.1.0 · Ray 8d ago
sn74ls14n-etched.step sn74ls14n: factory component page (tier=lcsc) · Ray 8d ago
sn74ls14n-hero.glb sn74ls14n: hero GLB from the etched model (keeps the MPN mark) · Ray 8d ago
sn74ls14n-hero.overlay.json Publish 0.1.0 · Ray 8d ago
sn74ls14n.glb Publish 0.1.0 · Ray 8d ago
sn74ls14n.kicad_mod Publish 0.1.0 · Ray 8d ago
sn74ls14n.kicad_sym Publish 0.1.0 · Ray 8d ago
sn74ls14n.lbr Publish 0.1.0 · Ray 8d ago
sn74ls14n.step Publish 0.1.0 · Ray 8d ago

SN74LS14N

lingxingic · Inverters · DIP-14

SN74LS14N from lingxingic, in a DIP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1A input Data input of inverter 1 (Schmitt-trigger input); the input voltage range is 0 V to VCC.
2 1Y output Data output of inverter 1, the logic inverse of 1A; output current is limited to ±25 mA absolute maximum.
3 2A input Data input of inverter 2 (Schmitt-trigger input); the input voltage range is 0 V to VCC.
4 2Y output Data output of inverter 2, the logic inverse of 2A; output current is limited to ±25 mA absolute maximum.
5 3A input Data input of inverter 3 (Schmitt-trigger input); the input voltage range is 0 V to VCC.
6 3Y output Data output of inverter 3, the logic inverse of 3A; output current is limited to ±25 mA absolute maximum.
7 GND power_in Ground reference, 0 V.
8 4Y output Data output of inverter 4, the logic inverse of 4A; output current is limited to ±25 mA absolute maximum.
9 4A input Data input of inverter 4 (Schmitt-trigger input); the input voltage range is 0 V to VCC.
10 5Y output Data output of inverter 5, the logic inverse of 5A; output current is limited to ±25 mA absolute maximum.
11 5A input Data input of inverter 5 (Schmitt-trigger input); the input voltage range is 0 V to VCC.
12 6Y output Data output of inverter 6, the logic inverse of 6A; output current is limited to ±25 mA absolute maximum.
13 6A input Data input of inverter 6 (Schmitt-trigger input); the input voltage range is 0 V to VCC.
14 VCC power_in Supply voltage; recommended 2.0 V to 6.0 V (typ. 5.0 V), absolute maximum -0.5 V to +7 V.

Key specifications

Parameter Value
Manufacturer lingxingic
Package DIP-14
Category Logic
Pins 14

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VCC -0.5 7 V 8
Input clamp current IIK -20 20 mA VI<-0.5V 或 VI>VCC+0.5V 8
Output clamp current IOK -20 20 mA VO<-0.5V 或 VO>VCC+0.5V 8
Output current IO -25 25 mA -0.5V<VO<VCC+0.5V 8
Supply current ICC 50 mA 8
Ground current IGND -50 mA 8
Total power dissipation Ptot 500 mW 8
Storage temperature Tstg -65 150 ℃ 8
Soldering temperature (DIP) TL 245 ℃ 10 s, DIP 8
Supply voltage (recommended) VCC 2 5 6 V 8
Input voltage VI 0 V 8
Output voltage VO 0 V 8
Operating ambient temperature Tamb -40 125 ℃ 8
High-level output voltage VOH 1.9 V VI=VT+或VT-；IO=-20uA；VCC=2.0V 11
High-level output voltage VOH 4.4 V VI=VT+或VT-；IO=-20uA；VCC=4.5V 11
High-level output voltage VOH 5.9 V VI=VT+或VT-；IO=-20uA；VCC=6.0V 11
High-level output voltage VOH 3.7 V VI=VT+或VT-；IO=-4.0mA；VCC=4.5V 11
High-level output voltage VOH 5.2 V VI=VT+或VT-；IO=-5.2mA；VCC=6.0V 11
Low-level output voltage VOL 0.1 V VI=VT+或VT-；IO=20uA；VCC=2.0V 11
Low-level output voltage VOL 0.4 V VI=VT+或VT-；IO=4.0mA；VCC=4.5V 11
Input leakage current II -1 1 uA VI=VCC或GND；VCC=6.0V 11
Quiescent supply current ICC 40 uA VI=VCC或GND；IO=0A；VCC=6.0V 11
Input capacitance CI 3.5 pF 9
Propagation delay nA to nY (tPLH, tPHL) tPLH，tPHL 190 ns 见图5；VCC=2.0V 13
Propagation delay nA to nY (tPLH, tPHL) tPLH，tPHL 38 ns 见图5；VCC=4.5V 13
Propagation delay nA to nY (tPLH, tPHL) tPLH，tPHL 32 ns 见图5；VCC=6.0V 13
Transition time (tTLH, tTHL) tTLH，tTHL 110 ns 见图5；VCC=2.0V 13
Transition time (tTLH, tTHL) tTLH，tTHL 22 ns 见图5；VCC=4.5V 13
Transition time (tTLH, tTHL) tTLH，tTHL 19 ns 见图5；VCC=6.0V 13
Positive threshold voltage VT+ 0.7 1.5 V VCC=2.0V 14
Positive threshold voltage VT+ 1.7 3.15 V VCC=4.5V 14
Positive threshold voltage VT+ 2.1 4.2 V VCC=6.0V 14
Negative threshold voltage VT- 0.3 0.9 V VCC=2.0V 14
Negative threshold voltage VT- 0.9 2 V VCC=4.5V 14
Negative threshold voltage VT- 1.2 2.6 V VCC=6.0V 14

CAD (KiCad official)

  • Symbol: SN74LS14N
  • Footprint: Package_DIP:DIP-14_W7.62mm
  • 3D model: DIP-14 (KiCad packages3D, STEP)
  • 3D model files: sn74ls14n-etched.step / sn74ls14n-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74ls14n.step / sn74ls14n.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: lingxingic datasheet (20 pp, sha256 e929eb7323870368, retrieved 2026-10-14, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF